| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 100 v16f32 = 45, // 16 x f32 enumerator in enum:llvm::MVT::SimpleValueType
225 return (SimpleTy == MVT::v8f64 || SimpleTy == MVT::v16f32 ||
294 case v16f32: return f32;
315 case v16f32: return 16;
405 case v16f32:
529 if (NumElements == 16) return MVT::v16f32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 254 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
255 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
256 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
257 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
281 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
282 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 163 case MVT::v16f32: return "v16f32";
226 case MVT::v16f32: return VectorType::get(Type::getFloatTy(Context), 16);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 104 case MVT::v16f32: return "MVT::v16f32";
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 61 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
