| /external/clang/test/CodeGen/ |
| mips-vector-arg.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
|
| mips-vector-return.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) {
29 return (v4i32){0, a, 0, 0};
|
| compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); typedef
7 v4i32 *y = &(v4i32){1,2,3,4};
|
| x86_32-arguments-darwin.c | 224 typedef int v4i32 __attribute__((__vector_size__(16))); typedef
228 v4i32 f55(v4i32 arg) { return arg+arg; }
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 180 { ISD::SHL, MVT::v4i32, 1 },
181 { ISD::SRL, MVT::v4i32, 1 },
182 { ISD::SRA, MVT::v4i32, 1 },
226 { ISD::SHL, MVT::v4i32, 1 }, // pslld
231 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
236 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
260 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
265 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
270 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
281 { ISD::SDIV, MVT::v4i32, 4*20 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 211 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
212 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
215 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
216 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
235 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
236 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
259 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
459 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
509 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}
[all...] |
| ARMISelLowering.cpp | 159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
467 addQRTypeForNEON(MVT::v4i32);
546 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
581 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
609 // It is legal to extload from v4i8 to v4i16 or v4i32.
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 84 v4i32 = 33, // 4 x i32 enumerator in enum:llvm::MVT::SimpleValueType
212 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
282 case v4i32:
326 case v4i32:
391 case v4i32:
511 if (NumElements == 4) return MVT::v4i32;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 62 (int)MVT::v4i32,
90 (int)MVT::v4i32,
504 INTTY = MVT::v4i32;
651 INTTY = MVT::v4i32;
669 INTTY = MVT::v4i32;
|
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 37 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
|
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 54 (int)MVT::v4i32,
79 (int)MVT::v4i32,
406 INTTY = MVT::v4i32;
551 INTTY = MVT::v4i32;
568 INTTY = MVT::v4i32;
|
| AMDGPUISelLowering.cpp | 65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
77 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
98 (int)MVT::v4i32
|
| R600ISelLowering.cpp | 34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
53 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
78 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
86 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 62 (int)MVT::v4i32,
90 (int)MVT::v4i32,
504 INTTY = MVT::v4i32;
651 INTTY = MVT::v4i32;
669 INTTY = MVT::v4i32;
|
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 37 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 90 DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
188 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
261 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 151 case MVT::v4i32: return "v4i32";
214 case MVT::v4i32: return VectorType::get(Type::getInt32Ty(Context), 4);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 379 // We promote all non-typed operations to v4i32.
381 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
383 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
385 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
387 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
389 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
391 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
448 setOperationAction(ISD::AND , MVT::v4i32, Legal);
449 setOperationAction(ISD::OR , MVT::v4i32, Legal);
450 setOperationAction(ISD::XOR , MVT::v4i32, Legal)
[all...] |
| PPCISelDAGToDAG.cpp | 631 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
642 else if (VecVT == MVT::v4i32)
656 else if (VecVT == MVT::v4i32)
669 else if (VecVT == MVT::v4i32)
694 // types (v16i8, v8i16, v4i32, and v4f32).
701 case MVT::v4i32:
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 92 case MVT::v4i32: return "MVT::v4i32";
|
