| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 178 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
188 { ISD::SHL, MVT::v4i64, 1 },
189 { ISD::SRL, MVT::v4i64, 1 },
199 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
205 { ISD::SDIV, MVT::v4i64, 4*20 },
209 { ISD::UDIV, MVT::v4i64, 4*20 },
303 { ISD::SUB, MVT::v4i64, 4 },
304 { ISD::ADD, MVT::v4i64, 4 },
305 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
307 // Because we believe v4i64 to be a legal type, we must also include th
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 89 v4i64 = 38, // 4 x i64 enumerator in enum:llvm::MVT::SimpleValueType
220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
287 case v4i64:
327 case v4i64:
398 case v4i64:
518 if (NumElements == 4) return MVT::v4i64;
|