| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 214 Branch(&ok, eq, t8, Operand(zero_reg));
326 Branch(&done, eq, t8, Operand(zero_reg));
329 Ret(eq, t8, Operand(zero_reg));
361 scratch, Operand(zero_reg));
430 nor(scratch, reg0, zero_reg);
531 Branch(miss, ne, at, Operand(zero_reg));
755 subu(at, zero_reg, rt.rm());
779 addiu(rd, zero_reg, j.imm32_);
781 ori(rd, zero_reg, j.imm32_);
962 Subu(at, zero_reg, Operand(1))
[all...] |
| builtins-mips.cc | 144 __ mov(scratch3, zero_reg);
221 ne, "array size is unexpectedly 0", array_size, Operand(zero_reg));
329 __ Branch(&argc_one_or_more, ne, a0, Operand(zero_reg));
352 __ Branch(¬_empty_array, ne, a2, Operand(zero_reg));
354 __ mov(a0, zero_reg); // Treat this as a call with argc of zero.
359 __ Branch(call_generic_code, eq, a3, Operand(zero_reg));
496 t0, Operand(zero_reg));
532 t0, Operand(zero_reg));
567 t0, Operand(zero_reg));
605 __ Branch(&no_arguments, eq, a0, Operand(zero_reg));
[all...] |
| code-stubs-mips.cc | 222 __ Assert(eq, message, a3, Operand(zero_reg));
475 __ subu(at, zero_reg, source_);
491 __ mov(mantissa, zero_reg);
706 __ Branch(&done, eq, int_scratch, Operand(zero_reg));
712 __ Branch(&skip_sub, ge, dst2, Operand(zero_reg));
713 __ Subu(int_scratch, zero_reg, int_scratch);
737 __ Branch(&fewer_than_20_useful_bits, lt, scratch2, Operand(zero_reg));
752 __ mov(dst1, zero_reg);
806 __ Branch(not_int32, ne, except_flag, Operand(zero_reg));
821 __ Branch(&done, eq, scratch1, Operand(zero_reg));
[all...] |
| lithium-codegen-mips.cc | 146 __ Branch(&ok, eq, t1, Operand(zero_reg));
167 __ Branch(&loop, ne, a0, Operand(zero_reg));
881 __ Branch(USE_DELAY_SLOT, &positive_dividend, ge, left, Operand(zero_reg));
882 __ subu(result, zero_reg, left);
885 DeoptimizeIf(eq, instr->environment(), result, Operand(zero_reg));
888 __ subu(result, zero_reg, result);
898 DeoptimizeIf(eq, instr->environment(), right, Operand(zero_reg));
901 __ Branch(USE_DELAY_SLOT, &done, ge, left, Operand(zero_reg));
905 DeoptimizeIf(eq, instr->environment(), result, Operand(zero_reg));
923 DeoptimizeIf(eq, instr->environment(), right, Operand(zero_reg));
[all...] |
| regexp-macro-assembler-mips.cc | 205 BranchOrBacktrack(¬_at_start, eq, a0, Operand(zero_reg));
218 BranchOrBacktrack(on_not_at_start, eq, a0, Operand(zero_reg));
302 __ Branch(&fallthrough, eq, a1, Operand(zero_reg));
306 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg));
393 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg));
413 __ Branch(&fallthrough, eq, a1, Operand(zero_reg));
417 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg));
566 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg));
579 BranchOrBacktrack(on_no_match, ne, a0, Operand(zero_reg));
644 __ Branch(&stack_limit_hit, le, a0, Operand(zero_reg));
[all...] |
| assembler-mips.cc | 116 0, // zero_reg
156 zero_reg,
586 // nop(type) == sll(zero_reg, zero_reg, type);
591 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
592 rs == static_cast<uint32_t>(ToNumber(zero_reg)) &&
1060 beq(zero_reg, zero_reg, offset);
1066 bgezal(zero_reg, offset);
1094 GenInstrImmediate(BGTZ, rs, zero_reg, offset)
[all...] |
| macro-assembler-mips.h | 172 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
173 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
193 Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) {
440 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as
455 // Return <n> if we have a sll zero_reg, zero_reg, n
458 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
459 rs == static_cast<uint32_t>(ToNumber(zero_reg)));
[all...] |
| codegen-mips.cc | 370 __ Branch(&check_sequential, eq, at, Operand(zero_reg));
375 __ Branch(&cons_string, eq, at, Operand(zero_reg));
408 __ Branch(&external_string, ne, at, Operand(zero_reg));
424 at, Operand(zero_reg));
429 __ Branch(call_runtime, ne, at, Operand(zero_reg));
436 __ Branch(&ascii, ne, at, Operand(zero_reg));
|
| full-codegen-mips.cc | 62 // marker is a andi zero_reg, rx, #yyyy instruction, and rx * 0x0000ffff + yyyy
65 // The marker instruction is effectively a NOP (dest is zero_reg) and will
87 __ Branch(target, eq, at, Operand(zero_reg));
98 __ Branch(target, ne, at, Operand(zero_reg));
105 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask);
166 __ Branch(&ok, eq, t1, Operand(zero_reg));
322 __ mov(v0, zero_reg);
373 __ slt(at, a3, zero_reg);
374 __ beq(at, zero_reg, &ok);
381 __ beq(at, zero_reg, &ok)
[all...] |
| stub-cache-mips.cc | 146 __ Branch(miss_label, ne, scratch0, Operand(zero_reg));
601 __ push(zero_reg);
670 __ sw(zero_reg, MemOperand(a1, 3 * kPointerSize));
[all...] |
| ic-mips.cc | 94 __ Branch(miss, ne, scratch1, Operand(zero_reg));
150 __ Branch(miss, ne, at, Operand(zero_reg));
204 __ Branch(miss, ne, at, Operand(zero_reg));
280 __ Branch(slow, ne, at, Operand(zero_reg));
371 __ Branch(index_string, eq, at, Operand(zero_reg));
378 __ Branch(not_symbol, eq, at, Operand(zero_reg));
771 __ Branch(slow_case, ne, scratch1, Operand(zero_reg));
[all...] |
| lithium-codegen-mips.h | 231 Register src1 = zero_reg,
232 const Operand& src2 = Operand(zero_reg));
|
| /external/chromium_org/v8/src/mips/ |
| macro-assembler-mips.cc | 234 Branch(&ok, eq, t8, Operand(zero_reg));
348 Branch(&done, eq, t8, Operand(zero_reg));
351 Ret(eq, t8, Operand(zero_reg));
383 scratch, Operand(zero_reg));
451 nor(scratch, reg0, zero_reg);
551 Branch(miss, ne, at, Operand(zero_reg));
775 subu(at, zero_reg, rt.rm());
817 addiu(rd, zero_reg, j.imm32_);
819 ori(rd, zero_reg, j.imm32_);
996 Subu(at, zero_reg, Operand(1))
[all...] |
| lithium-codegen-mips.cc | 155 __ Branch(&ok, eq, t1, Operand(zero_reg));
794 __ Branch(&no_deopt, ne, a1, Operand(zero_reg));
[all...] |
| code-stubs-mips.cc | 454 __ Assert(eq, kExpected0AsASmiSentinel, a3, Operand(zero_reg));
540 __ subu(at, zero_reg, source_);
556 __ mov(mantissa, zero_reg);
608 __ ctc1(zero_reg, FCSR);
625 __ Branch(&done, eq, scratch, Operand(zero_reg));
644 __ Movz(result_reg, zero_reg, scratch);
645 __ Branch(&done, eq, scratch, Operand(zero_reg));
654 __ Branch(&normal_exponent, le, result_reg, Operand(zero_reg));
655 __ mov(result_reg, zero_reg);
672 __ mov(input_high, zero_reg);
[all...] |
| regexp-macro-assembler-mips.cc | 212 BranchOrBacktrack(¬_at_start, ne, a0, Operand(zero_reg));
225 BranchOrBacktrack(on_not_at_start, ne, a0, Operand(zero_reg));
260 __ Branch(&fallthrough, eq, a1, Operand(zero_reg));
264 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg));
357 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg));
377 __ Branch(&fallthrough, eq, a1, Operand(zero_reg));
381 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg));
421 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c);
430 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c);
479 BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg));
[all...] |
| lithium-codegen-mips.h | 256 Register src1 = zero_reg,
257 const Operand& src2 = Operand(zero_reg));
260 Register src1 = zero_reg,
261 const Operand& src2 = Operand(zero_reg));
264 Register src1 = zero_reg,
265 const Operand& src2 = Operand(zero_reg));
|
| builtins-mips.cc | 127 t0, Operand(zero_reg));
157 t0, Operand(zero_reg));
193 __ Branch(&no_arguments, eq, a0, Operand(zero_reg));
236 t0, Operand(zero_reg));
262 __ Branch(&convert_argument, ne, t0, Operand(zero_reg));
390 __ Branch(&rt_call, ne, a2, Operand(zero_reg));
417 __ Branch(&allocate, ne, t0, Operand(zero_reg));
500 __ Branch(&allocated, eq, a3, Operand(zero_reg));
502 a3, Operand(zero_reg));
624 __ Branch(&loop, greater_equal, a3, Operand(zero_reg));
[all...] |
| assembler-mips.cc | 144 0, // zero_reg
184 zero_reg,
578 // Traditional mips nop == sll(zero_reg, zero_reg, 0)
579 // When marking non-zero type, use sll(zero_reg, at, type)
583 Register nop_rt_reg = (type == 0) ? zero_reg : at;
585 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
1065 beq(zero_reg, zero_reg, offset);
1071 bgezal(zero_reg, offset)
[all...] |
| code-stubs-mips.h | 296 masm->instr_at_put(pos, BNE | (zero_reg.code() << kRsShift) |
297 (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
303 masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) |
304 (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
|
| full-codegen-mips.cc | 62 // marker is a andi zero_reg, rx, #yyyy instruction, and rx * 0x0000ffff + yyyy
65 // The marker instruction is effectively a NOP (dest is zero_reg) and will
87 __ Branch(target, eq, at, Operand(zero_reg));
98 __ Branch(target, ne, at, Operand(zero_reg));
105 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask);
161 __ Branch(&ok, eq, t1, Operand(zero_reg));
192 __ Branch(&loop, gt, a2, Operand(zero_reg));
330 __ mov(v0, zero_reg);
376 __ slt(at, a3, zero_reg);
377 __ beq(at, zero_reg, &ok)
[all...] |
| macro-assembler-mips.h | 179 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
180 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
200 Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) {
452 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as
467 // Return <n> if we have a sll zero_reg, zero_reg, n
470 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
471 rs == static_cast<uint32_t>(ToNumber(zero_reg)));
[all...] |
| ic-mips.cc | 94 __ Branch(miss, ne, scratch1, Operand(zero_reg));
150 __ Branch(miss, ne, at, Operand(zero_reg));
204 __ Branch(miss, ne, at, Operand(zero_reg));
233 __ Branch(slow, ne, at, Operand(zero_reg));
327 __ Branch(index_string, eq, at, Operand(zero_reg));
335 __ Branch(not_unique, ne, at, Operand(zero_reg));
739 __ Branch(slow_case, ne, scratch1, Operand(zero_reg));
[all...] |
| codegen-mips.cc | 438 __ Branch(&check_sequential, eq, at, Operand(zero_reg));
443 __ Branch(&cons_string, eq, at, Operand(zero_reg));
476 __ Branch(&external_string, ne, at, Operand(zero_reg));
492 at, Operand(zero_reg));
497 __ Branch(call_runtime, ne, at, Operand(zero_reg));
504 __ Branch(&ascii, ne, at, Operand(zero_reg));
|
| /art/compiler/dex/quick/ |
| gen_loadstore.cc | 43 void Mir2Lir::Workaround7250540(RegLocation rl_dest, int zero_reg) {
58 int temp_reg = zero_reg;
70 if (zero_reg == INVALID_REG) {
|
