| /prebuilts/ndk/9/platforms/android-9/arch-arm/usr/include/asm/ |
| byteorder.h | 25 __asm__ ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
|
| /external/antlr/antlr-3.4/runtime/Ruby/test/unit/ |
| test-scheme.rb | 34 0 => "<invalid>", -1 => "<EOF>", 1 => "<EOR>",
54 0 => "<invalid>", -1 => "<EOF>", 1 => "<EOR>",
|
| /external/llvm/test/MC/ARM/ |
| arm-arithmetic-aliases.s | 46 eor r2, r2, #6 label
47 eor r2, #6 label
48 eor r2, r2, r3 label
49 eor r2, r3 label
51 @ CHECK: eor r2, r2, #6 @ encoding: [0x06,0x20,0x22,0xe2]
52 @ CHECK: eor r2, r2, #6 @ encoding: [0x06,0x20,0x22,0xe2]
53 @ CHECK: eor r2, r2, r3 @ encoding: [0x03,0x20,0x22,0xe0]
54 @ CHECK: eor r2, r2, r3 @ encoding: [0x03,0x20,0x22,0xe0]
|
| /external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/ |
| sha256-armv4.pl | 69 eor $t0,$t0,$e,ror#$Sigma1[1]
70 eor $t1,$f,$g
79 eor $t0,$t0,$e,ror#$Sigma1[2] @ Sigma1(e)
83 eor $t1,$t1,$g @ Ch(e,f,g)
87 eor $h,$h,$a,ror#$Sigma0[1]
89 eor $h,$h,$a,ror#$Sigma0[2] @ Sigma0(a)
111 eor $t0,$t0,$t3,ror#$sigma0[1]
113 eor $t0,$t0,$t3,lsr#$sigma0[2] @ sigma0(X[i+1])
116 eor $t3,$t3,$t2,ror#$sigma1[1]
118 eor $t3,$t3,$t2,lsr#$sigma1[2] @ sigma1(X[i+14]
[all...] |
| sha1-thumb.pl | 70 eor $t1,$d
72 eor $t1,$d @ F_00_19(B,C,D)
81 eor $t1,$c
82 eor $t1,$d @ F_20_39(B,C,D)
161 eor $a,$b
162 eor $a,$c
163 eor $a,$d
|
| sha1-armv4-large.pl | 82 eor $t0,$t0,$t1
83 eor $t2,$t2,$t3 @ 1 cycle stall
84 eor $t1,$c,$d @ F_xx_xx
87 eor $t0,$t0,$t2,ror#31
105 eor $t1,$c,$d @ F_xx_xx
112 eor $t1,$c,$d @ F_xx_xx
120 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
130 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
137 &Xupdate(@_,"eor $t1,$b,$t1,ror#2");
|
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| loopfilter_v6.asm | 172 eor r7, r7, r12 ; p1 offset to convert to a signed value
173 eor r8, r8, r12 ; p0 offset to convert to a signed value
174 eor r9, r9, r12 ; q0 offset to convert to a signed value
175 eor r10, r10, r12 ; q1 offset to convert to a signed value
240 eor r11, r11, r12 ; *op1 = u^0x80
242 eor r9, r9, r12 ; *op0 = u^0x80
244 eor r8, r8, r12 ; *oq0 = u^0x80
246 eor r10, r10, r12 ; *oq1 = u^0x80
383 eor r7, r7, r12 ; ps1
384 eor r8, r8, r12 ; ps
[all...] |
| vp8_variance_halfpixvar16x16_h_armv6.asm | 46 eor r4, r4, r10
76 eor r4, r4, r10
107 eor r4, r4, r10
138 eor r4, r4, r10
|
| vp8_variance_halfpixvar16x16_v_armv6.asm | 47 eor r4, r4, r10
77 eor r4, r4, r10
108 eor r4, r4, r10
139 eor r4, r4, r10
|
| /external/openssl/crypto/sha/asm/ |
| sha256-armv4.pl | 69 eor $t0,$t0,$e,ror#$Sigma1[1]
70 eor $t1,$f,$g
79 eor $t0,$t0,$e,ror#$Sigma1[2] @ Sigma1(e)
83 eor $t1,$t1,$g @ Ch(e,f,g)
87 eor $h,$h,$a,ror#$Sigma0[1]
89 eor $h,$h,$a,ror#$Sigma0[2] @ Sigma0(a)
111 eor $t0,$t0,$t3,ror#$sigma0[1]
113 eor $t0,$t0,$t3,lsr#$sigma0[2] @ sigma0(X[i+1])
116 eor $t3,$t3,$t2,ror#$sigma1[1]
118 eor $t3,$t3,$t2,lsr#$sigma1[2] @ sigma1(X[i+14]
[all...] |
| sha1-thumb.pl | 70 eor $t1,$d
72 eor $t1,$d @ F_00_19(B,C,D)
81 eor $t1,$c
82 eor $t1,$d @ F_20_39(B,C,D)
161 eor $a,$b
162 eor $a,$c
163 eor $a,$d
|
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 116 COMPARE(eor(r4, r5, Operand(r6, LSL, 0)),
117 "e0254006 eor r4, r5, r6");
118 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
120 COMPARE(eor(r4, r5, Operand(r8, LSL, 2), LeaveCC, ne),
122 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
276 // We only disassemble one instruction so the eor instruction is not here.
277 COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne),
283 // We only disassemble one instruction so the eor instruction is not here.
284 // The eor does the setcc so we get a movw here.
285 COMPARE(eor(r5, r4, Operand(0x1234), SetCC, ne)
[all...] |
| /frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
| sad_inline.h | 192 EOR x7, src2, src1; /* check odd/even combination */
194 EOR x7, x7, src1;
199 EOR src1, src1, x7, asr #7; /* take absolute value of negative byte */
211 EOR x7, src2, src1; /* check odd/even combination */
213 EOR x7, x7, src1; /* only odd bytes need to add carry */
217 EOR src1, src1, x7, asr #7; /* take absolute value of negative byte */
360 "EOR %1, %2, %0\n\t"
362 "EOR %1, %1, %0\n\t"
367 "EOR %0, %0, %1, asr #7"
380 "EOR %1, %2, %0\n\t
[all...] |
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 195 EOR x7, src2, src1; /* check odd/even combination */
197 EOR x7, x7, src1;
202 EOR src1, src1, x7, asr #7; /* take absolute value of negative byte */
214 EOR x7, src2, src1; /* check odd/even combination */
216 EOR x7, x7, src1; /* only odd bytes need to add carry */
220 EOR src1, src1, x7, asr #7; /* take absolute value of negative byte */
373 asm volatile("eor %0, %3, %2\n\t"
375 "eor %0, %0, %1\n\t"
380 "eor %1, %1, %0, asr #7"
398 asm volatile("eor %1, %3, %2\n\t
[all...] |
| /sdk/emulator/qtools/ |
| opcode.cpp | 123 "eor",
177 "eor",
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm.cc | 112 COMPARE(eor(r4, r5, Operand(r6, LSL, 0)),
113 "e0254006 eor r4, r5, r6");
114 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
116 COMPARE(eor(r4, r5, Operand(r8, LSL, 2), LeaveCC, ne),
118 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
272 // We only disassemble one instruction so the eor instruction is not here.
273 COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne),
283 // We only disassemble one instruction so the eor instruction is not here.
284 // The eor does the setcc so we get a movw here.
285 COMPARE(eor(r5, r4, Operand(0x1234), SetCC, ne)
[all...] |
| /external/compiler-rt/lib/arm/ |
| negdf2vfp.S | 21 eor r1, r1, #-2147483648 // flip sign bit on double in r0/r1 pair
|
| negsf2vfp.S | 21 eor r0, r0, #-2147483648 // flip sign bit on float in r0
|
| /external/libvpx/libvpx/vp8/encoder/arm/armv6/ |
| vp8_fast_quantize_b_armv6.asm | 48 eor r9, r9, lr ; [z1 ^ sz1 | z0 ^ sz0]
60 eor r12, r12, r11 ; [z3 ^ sz3 | z2 ^ sz2]
67 eor r0, r0, lr ; [(y1 ^ sz1) | (y0 ^ sz0)]
81 eor r10, r10, r11 ; [(y3 ^ sz3) | (y2 ^ sz2)]
|
| /external/llvm/test/CodeGen/ARM/ |
| bits.ll | 22 ; CHECK: eor r0, r1, r0
|
| /external/llvm/test/CodeGen/AArch64/ |
| logical_shifted_reg.ll | 14 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
32 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
57 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
71 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #10
81 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
104 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
122 ; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
147 ; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
161 ; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #10
171 ; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #
[all...] |
| /bionic/libc/arch-arm/bionic/ |
| strcmp.S | 57 eor r2, r0, r1
76 eor r2, r2, #3
185 eor t1, t1, w1
233 eor t1, t1, w1
278 eor t1, t1, w1
|
| /bionic/libc/arch-arm/generic/bionic/ |
| strcmp.S | 57 eor r2, r0, r1
76 eor r2, r2, #3
185 eor t1, t1, w1
233 eor t1, t1, w1
278 eor t1, t1, w1
|
| /external/llvm/test/MC/AArch64/ |
| neon-bitwise-instructions.s | 26 // Vector Eor
28 eor v0.8b, v1.8b, v2.8b
29 eor v0.16b, v1.16b, v2.16b
31 // CHECK: eor v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x2e]
32 // CHECK: eor v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x6e]
|
| /external/chromium_org/third_party/openssl/openssl/patches/ |
| neon_runtime.patch | 298 + eor sl, sl, r8
304 + eor r6, r6, r8
305 + eor r9, r9, r4
310 + eor ip, ip, fp
357 + eor sl, r6, sl
359 + eor ip, fp, ip
361 + eor r9, r6, r9
365 + eor r8, r6, r8
415 + eor sl, r6, sl
418 + eor r8, fp, r
[all...] |
