| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 44 setOperationAction(ISD::ADD, MVT::i64, Legal);
45 setOperationAction(ISD::ADD, MVT::i32, Legal);
52 // add the SGPRs as livein registers.
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| SCCP.java | 98 * @param ssaBlock Block to add
102 cfgWorklist.add(ssaBlock);
105 cfgPhiWorklist.add(ssaBlock);
117 varyingWorklist.add(insn);
121 ssaWorklist.add(insn);
337 * If condition is constant, add only the target block to the
338 * worklist. Otherwise, add all successors to the worklist.
350 branchWorklist.add(insn);
406 case RegOps.ADD:
509 case RegOps.ADD
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 302 { ISD::ADD, MVT::v8i32, 4 },
304 { ISD::ADD, MVT::v4i64, 4 },
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 44 setOperationAction(ISD::ADD, MVT::i64, Legal);
45 setOperationAction(ISD::ADD, MVT::i32, Legal);
52 // add the SGPRs as livein registers.
|
| /external/pixman/pixman/ |
| pixman-fast-path.c | [all...] |
| pixman-arm-simd.c | 228 PIXMAN_STD_FAST_PATH (ADD, a8, null, a8, armv6_composite_add_8_8),
|
| /ndk/sources/host-tools/nawk-20071023/ |
| awkgram.y | 57 %token <i> ADD MINUS MULT DIVIDE MOD
353 | term '+' term { $$ = op2(ADD, $1, $3); }
|
| /external/chromium/chrome/browser/sync/glue/ |
| autofill_profile_change_processor.cc | 132 case AutofillProfileChange::ADD: {
225 LOG(ERROR) << "could not add autofill profile for guid " << p.guid();
309 notification_registrar_.Add(this,
|
| /external/chromium_org/components/dom_distiller/core/ |
| dom_distiller_store.cc | 218 article_update.update_type = DomDistillerObserver::ArticleUpdate::ADD;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 188 #define CHECK( NM, FLAG, ADD ) \
191 return FLAG ? atom->cmd_size + (ADD) : 0; \
194 #define TCL_CHECK( NM, FLAG, ADD ) \
198 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| program_lexer.l | 187 ADD{sz}{cc}{sat} { return_opcode( 1, BIN_OP, ADD, 3); }
|
| /external/chromium_org/v8/test/mjsunit/ |
| stack-traces.js | 290 // Omitted because ADD from runtime.js is non-native builtin.
291 testOmittedBuiltin(function(){ thrower + 2; }, "ADD");
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 202 // Operand is a result from an ADD.
203 if (Addr.getOpcode() == ISD::ADD) {
258 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 95 if (Addr.getOpcode() == ISD::ADD) {
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 188 #define CHECK( NM, FLAG, ADD ) \
191 return FLAG ? atom->cmd_size + (ADD) : 0; \
194 #define TCL_CHECK( NM, FLAG, ADD ) \
198 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
[all...] |
| /external/mesa3d/src/mesa/program/ |
| program_lexer.l | 187 ADD{sz}{cc}{sat} { return_opcode( 1, BIN_OP, ADD, 3); }
|
| /external/v8/src/arm/ |
| constants-arm.h | 195 ADD = 4 << 21, // Add.
196 ADC = 5 << 21, // Add with Carry.
445 // add(sp, sp, 4) instruction (aka Pop())
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_DeblockingLuma_unsafe_s.s | 238 ADD alpha, alpha, m01, LSL #1
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 120 ADD r12, pSrc, srcStep, LSL #2
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_Interpolate_Chroma_s.S | 50 P0: ADD pc,r11
|
| /external/v8/src/ia32/ |
| code-stubs-ia32.cc | 547 __ add(esp, Immediate(kDoubleSize * XMMRegister::kNumRegisters));
697 __ add(esp, Immediate(sizeof(uint64_t))); // Nolint.
808 stream->Add("UnaryOpStub_%s_%s_%s",
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| pred_lt4_1_opt.s | 41 ADD r5, r0, r4, LSL #1 @x = exc - T0
49 ADD r6, r8
52 ADD r8, r6, r8 @ptr2 = &(inter4_2[k][0])
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv30/ |
| nvfx_fragprog.c | 483 nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none));
535 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
583 nvfx_fp_emit(fpc, arith(0, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
594 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
771 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
[all...] |
| /external/mesa3d/src/gallium/drivers/nv30/ |
| nvfx_fragprog.c | 483 nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none));
535 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
583 nvfx_fp_emit(fpc, arith(0, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
594 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
771 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 97 case ISD::ADD:
554 case ISD::ADD:
785 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
827 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
[all...] |
