| /external/llvm/lib/Target/Mips/ |
| MipsMCInstLower.cpp | 138 return MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 566 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
571 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
633 MI.insert(I, MCOperand::CreateReg(0));
635 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
643 MI.insert(I, MCOperand::CreateReg(0));
645 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 391 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
396 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
401 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
406 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
425 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
430 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
435 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
440 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
445 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
450 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]))
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 864 Inst.addOperand(MCOperand::CreateReg(getReg()));
918 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
920 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
922 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
942 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
|
| ExpandPostRAPseudos.cpp | 74 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
|
| MachineInstr.cpp | 523 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
526 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
[all...] |
| LiveDebugVariables.cpp | 764 MachineOperand MO = MachineOperand::CreateReg(LI->reg, false);
[all...] |
| RegisterCoalescer.cpp | 852 NewMI->addOperand(MachineOperand::CreateReg(CopyDstReg,
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 131 static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
231 Inst.addOperand(MCOperand::CreateReg(getReg()));
245 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
251 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
253 Inst.addOperand(MCOperand::CreateReg(Mem.Index));
258 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
500 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 41 NopInst.addOperand(MCOperand::CreateReg(0));
467 MI.addOperand(MachineOperand::CreateReg(0, false));
498 MI.addOperand(MachineOperand::CreateReg(0, false));
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCMCInstLower.cpp | 177 MCOp = MCOperand::CreateReg(MO.getReg());
|
| PPCInstrInfo.cpp | 271 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
282 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
320 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
334 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 210 /// CreateReg - Allocate a single virtual register for the given type.
211 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
236 unsigned R = CreateReg(RegisterVT);
|
| FastISel.cpp | 624 Op = MachineOperand::CreateReg(Reg, false);
640 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 230 MI.addOperand(MachineOperand::CreateReg(
|
| R600InstrInfo.cpp | 658 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
678 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 68 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
|
| MachineOperand.h | 560 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 218 Inst.addOperand(MCOperand::CreateReg(Reg));
230 Inst.addOperand(MCOperand::CreateReg(Reg));
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 790 static AArch64Operand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
894 Inst.addOperand(MCOperand::CreateReg(getReg()));
[all...] |
