| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Syn_filt_32_neon.s | 52 VLD1.S16 {D0, D1, D2, D3}, [r0]! @a[1] ~ a[16]
58 VREV64.16 D1, D1
71 VMLAL.S16 Q10, D10, D1
87 VMLAL.S16 Q11, D6, D1
|
| residu_asm_neon.s | 36 VLD1.S16 {D0, D1, D2, D3}, [r0]! @get all a[]
61 VQDMLAL.S16 Q10, D5, D1[0]
65 VQDMLAL.S16 Q10, D5, D1[1]
69 VQDMLAL.S16 Q10, D5, D1[2]
73 VQDMLAL.S16 Q10, D5, D1[3]
|
| Norm_Corr_neon.s | 79 VMLAL.S16 Q10, D1, D1
122 VMLAL.S16 Q10, D1, D1
123 VMLAL.S16 Q11, D1, D9
143 VMLAL.S16 Q10, D1, D1
144 VMLAL.S16 Q11, D1, D9
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_TransformResidual4x4_s.s | 60 dIn1 DN D1.S16
73 df1 DN D1.S16
87 dh1 DN D1.S16
124 VSUB de2,dIn1RS,dIn3 ;// e2 = (d1>>1) - d3
125 VADD de3,dIn1,dIn3RS ;// e3 = d1 + (d3>>1)
151 VSUB dg2,df1RS,df3 ;// e2 = (d1>>1) - d3
152 VADD dg3,df1,df3RS ;// e3 = d1 + (d3>>1)
|
| omxVCM4P10_TransformDequantLumaDCFromPair_s.s | 66 dIn1 DN D1.S16
78 dRowOp1 DN D1.S16
92 dColOp1 DN D1.S16
106 dOut1 DN D1.S16
|
| armVCM4P10_Interpolate_Chroma_s.s | 68 dRow0b DN D1.U8
107 dOut1U64 DN D1.U64
110 dOut01U32 DN D1.U32
115 dOut1U16 DN D1.U16
|
| omxVCM4P10_TransformDequantChromaDCFromPair_s.s | 66 dScale DN D1.S16
|
| /external/chromium/chrome/browser/chromeos/login/ |
| rounded_view.h | 41 template<typename D1, typename D2>
42 RoundedView(const D1& val1, const D2& val2) : C(val1, val2) {}
|
| /art/compiler/utils/arm/ |
| managed_register_arm_test.cc | 138 reg = ArmManagedRegister::FromDRegister(D1);
145 EXPECT_EQ(D1, reg.AsDRegister());
313 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromDRegister(D1)));
323 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromDRegister(D1)));
333 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromDRegister(D1)));
343 EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromDRegister(D1)));
353 EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromDRegister(D1)));
363 EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::FromDRegister(D1)));
373 EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromDRegister(D1)));
385 EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromDRegister(D1)));
[all...] |
| /external/llvm/test/MC/MachO/ |
| x86_32-symbols.s | 8 D1:
709 // CHECK: ('_string', 'D1')
|
| x86_64-symbols.s | 8 D1:
666 // CHECK: ('_string', 'D1')
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/comm/src/ |
| omxVCCOMM_Copy8x8_s.s | 38 X1 DN D1.S8
|
| omxVCCOMM_Copy16x16_s.s | 37 X1 DN D1.S8
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CStringSyntaxChecker.cpp | 39 if (const DeclRefExpr *D1 = dyn_cast<DeclRefExpr>(A1->IgnoreParenCasts()))
41 return D1->getDecl() == D2->getDecl();
|
| /external/clang/test/CXX/temp/temp.param/ |
| p15-cxx0x.cpp | 101 using D1 = drop<3, int, char, double, long>::type;
102 using D1 = types<long>;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 66 Hexagon::D0, Hexagon::D1, Hexagon::D2
122 Hexagon::D0, Hexagon::D1, Hexagon::D2
|
| /external/llvm/unittests/Support/ |
| AlignOfTest.cpp | 61 struct D1 : S1 {};
69 struct D9 : S1, D1 { S1 s1; };
117 [AlignOf<D1>::Alignment > 0]
158 EXPECT_LE(alignOf<S1>(), alignOf<D1>());
236 EXPECT_EQ(alignOf<D1>(), alignOf<AlignedCharArrayUnion<D1> >());
291 EXPECT_EQ(sizeof(D1), sizeof(AlignedCharArrayUnion<D1>));
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| armVCM4P2_Clip8_s.s | 33 dx01 DN D1.S16
|
| omxVCM4P2_QuantInvInter_I_s.s | 77 dMinusQP1 DN D1.S16
|
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 352 unsigned &D1, unsigned &D2, unsigned &D3) {
355 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
389 unsigned D0, D1, D2, D3;
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
464 unsigned D0, D1, D2, D3;
465 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
468 MIB.addReg(D1, getUndefRegState(SrcIsUndef))
[all...] |
| /external/clang/lib/AST/ |
| ASTImporter.cpp | 229 bool IsStructurallyEquivalent(Decl *D1, Decl *D2);
262 Decl *D1, Decl *D2);
[all...] |
| /external/v8/test/mjsunit/harmony/ |
| module-parsing.js | 82 module D1 = B.C.D
145 export A, A1, A2, A3, B, I, C1, D1, D2, D3, E1, E2, E3, X, Y, Z, Wrap, x, y, UU
|
| /external/libvpx/libvpx/vp9/common/x86/ |
| vp9_intrapred_ssse3.asm | 465 ; A1 B1 C1 D1
469 X_PLUS_2Y_PLUS_Z_PLUS_2_RSH_2 m0, m1, m2, m3 ; 3-tap avg B4 B3 B2 B1 C1 D1
472 punpcklqdq m3, m1 ; B4 B3 B2 B1 C1 D1 x x A4 A3 A2 A1 ..
476 pshufb m3, [GLOBAL(sh_b8091a2b345)] ; A4 B4 A3 B3 A2 B2 A1 B1 C1 D1 ..
478 psrldq m3, 2 ; A3 B3 A2 B2 A1 B1 C1 D1 ..
480 psrldq m3, 2 ; A2 B2 A1 B1 C1 D1 ..
482 psrldq m3, 2 ; A1 B1 C1 D1 ..
499 ; A1 B1 C1 D1 E1 F1 G1 H1
500 ; A2 B2 A1 B1 C1 D1 E1 F1
501 ; A3 B3 A2 B2 A1 B1 C1 D1
[all...] |
| /external/chromium_org/third_party/opus/src/celt/ |
| mathops.h | 191 #define D1 22804
199 return ADD16(D0, MULT16_16_Q15(frac, ADD16(D1, MULT16_16_Q15(frac, ADD16(D2 , MULT16_16_Q15(D3,frac))))));
|
| /external/clang/test/SemaCXX/ |
| cxx1y-variable-templates_in_class.cpp | 139 class D1 {
144 template<typename U> U* D1<T>::Data<U*> = (U*)(0);
150 //template<typename U> U* D1<float>::Data<U*> = (U*)(0) + 1;
152 //template int* D1<float>::Data<int*>;
|
