| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_clip.h | 78 struct brw_reg R0;
|
| brw_clip_line.c | 53 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
155 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
|
| brw_clip_unfilled.c | 222 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
235 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
243 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
|
| brw_clip_tri.c | 58 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
143 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
181 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
597 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
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| /external/openssl/crypto/md5/ |
| md5_locl.h | 112 #define R0(a,b,c,d,k,s,t) { \
|
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ClassCastExceptionTest.java | 157 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
162 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
|
| /art/compiler/utils/arm/ |
| assembler_arm.cc | 85 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
89 if (rhs >= R0 && rhs <= PC) {
327 EmitType01(cond, so.type(), TST, 1, rn, R0, so);
333 EmitType01(cond, so.type(), TEQ, 1, rn, R0, so);
338 EmitType01(cond, so.type(), CMP, 1, rn, R0, so);
343 EmitType01(cond, so.type(), CMN, 1, rn, R0, so);
360 EmitType01(cond, so.type(), MOV, 0, R0, rd, so);
365 EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
376 EmitType01(cond, so.type(), MVN, 0, R0, rd, so);
381 EmitType01(cond, so.type(), MVN, 1, R0, rd, so)
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Deemph_32_opt.s | 26 @x_hi RN R0
38 LDRSH r6, [r0], #2 @load x_hi[0]
50 LDRSH r6, [r0], #2 @load x_hi[1]
69 LDRSH r6, [r0], #2 @load x_hi[]
77 LDRSH r6, [r0], #2 @load x_hi[]
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Deemph_32_neon.s | 26 @x_hi RN R0
38 LDRSH r6, [r0], #2 @load x_hi[0]
50 LDRSH r6, [r0], #2 @load x_hi[1]
69 LDRSH r6, [r0], #2 @load x_hi[]
77 LDRSH r6, [r0], #2 @load x_hi[]
|
| /frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
| intra_est.cpp | 734 int P0, Q0, R0, S0, P1, Q1, R1, P2, Q2;
736 int r0, r1, r2, r3, r4, r5, r6, r7; local
863 temp |= (Q0 << 16); // [Q0 Q1 R0 DO]
864 temp |= (Q1 << 24); // [R0 D0 D1 D1]
868 R0 = (P_K + P_L + 1) >> 1;
871 temp |= (R0 << 16);
877 temp = R0 | (D0 << 8);
929 r0 = P_A;
934 r0 += (r1 << 1);
935 r0 += r2
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_clip_line.c | 53 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
155 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
|
| brw_clip_unfilled.c | 222 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
235 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
243 brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
|
| brw_clip_tri.c | 58 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
143 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
181 brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK));
597 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 256 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
265 // When used as the base register, r0 reads constant zero rather than
267 // assembler requires that we print r0 as 0 (no r) when used as the base.
268 if (MI->getOperand(OpNo).getReg() == PPC::R0)
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 138 SC2(r0,R0);
317 REST(r0,R0);
|
| /external/libvpx/libvpx/vp8/encoder/ppc/ |
| fdct_altivec.asm | 15 .macro load_c V, LABEL, OFF, R0, R1
16 lis \R0, \LABEL@ha
17 la \R1, \LABEL@l(\R0)
96 stw r0, 0(r8)
97 lwz r0, 4(r3)
98 stw r0, 4(r8)
99 lwzux r0, r3,r5
100 stw r0, 8(r8)
101 lwz r0, 4(r3)
102 stw r0, 12(r8
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/rtasm/ |
| rtasm_x86sse.c | 99 #define DUMP_R( R0 ) do { \
101 x86_print_reg( R0 ); \
104 #define DUMP_RR( R0, R1 ) do { \
106 x86_print_reg( R0 ); \
111 #define DUMP_RI( R0, I ) do { \
113 x86_print_reg( R0 ); \
117 #define DUMP_RRI( R0, R1, I ) do { \
119 x86_print_reg( R0 ); \
131 #define DUMP_R( R0 )
132 #define DUMP_RR( R0, R1
[all...] |
| /external/mesa3d/src/gallium/auxiliary/rtasm/ |
| rtasm_x86sse.c | 99 #define DUMP_R( R0 ) do { \
101 x86_print_reg( R0 ); \
104 #define DUMP_RR( R0, R1 ) do { \
106 x86_print_reg( R0 ); \
111 #define DUMP_RI( R0, I ) do { \
113 x86_print_reg( R0 ); \
117 #define DUMP_RRI( R0, R1, I ) do { \
119 x86_print_reg( R0 ); \
131 #define DUMP_R( R0 )
132 #define DUMP_RR( R0, R1
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 580 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = 0) {
582 RegUnits.back().Roots[0] = R0;
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
57 LIST(R0), LIST(R1), LIST(R2), LIST(R3), LIST(R4), LIST(R5), LIST(R6),
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 207 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
212 case R0: case R1: case R2: case R3:
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 101 unsigned Reg = Hexagon::R0;
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 149 GENOFFSET(ARM,arm,R0);
|
| /external/libvpx/libvpx/vp8/common/ppc/ |
| filter_bilinear_altivec.asm | 17 .macro load_c V, LABEL, OFF, R0, R1
18 lis \R0, \LABEL@ha
19 la \R1, \LABEL@l(\R0)
45 load_c v20, hfilter_b, r5, r9, r0
49 load_c v28, b_hperm_b, 0, r9, r0
220 lwz r0, 0(r1)
221 stw r0, 0(r7)
225 lwz r0, 0(r1)
226 stw r0, 0(r7)
230 lwz r0, 0(r1
[all...] |
| /external/chromium_org/third_party/mesa/src/docs/OLD/ |
| MESA_program_debug.spec | 312 be used to print the values of R0, R1, R2 and R3 while executing
|
