| /external/v8/src/mips/ |
| constants-mips.h | 305 SRL = ((0 << 3) + 2),
|
| assembler-mips.cc | 1298 void Assembler::srl(Register rd, Register rt, uint16_t sa) { function in class:v8::Assembler
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 72 setTargetDAGCombine(ISD::SRL);
507 case ISD::SRL:
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 747 case ISD::SRL:
759 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
764 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
| X86ISelDAGToDAG.cpp | 776 if (Shift.getOpcode() != ISD::SRL ||
790 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
791 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
801 InsertDAGNode(DAG, N, Srl);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| SelectionDAGBuilder.h | 488 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
| SelectionDAGDumper.cpp | 170 case ISD::SRL: return "srl";
|
| LegalizeTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | 115 case ISD::SRL:
569 case ISD::SRL:
[all...] |
| SelectionDAG.cpp | [all...] |
| /external/libffi/src/mips/ |
| o32.S | 80 SRL t2, t0, 4 # shift our arg info
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 113 setOperationAction(ISD::SRL, VT, Expand);
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| R600ISelLowering.cpp | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 315 void SRL(int Rd, int Rt, int shft);
|
| /external/llvm/lib/TableGen/ |
| Record.cpp | 941 case SRL: {
952 case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
978 case SRL: Result = "!srl"; break;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 130 setOperationAction(ISD::SRL, VT, Custom);
595 setTargetDAGCombine(ISD::SRL);
662 setOperationAction(ISD::SRL, MVT::i64, Custom);
[all...] |
| ARMISelDAGToDAG.cpp | 346 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
350 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
352 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
382 // Look for (and (srl X, c1), c2).
383 SDValue Srl = N1.getOperand(0);
385 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
404 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 623 case PPCISD::SRL: return "PPCISD::SRL";
[all...] |
| /external/chromium_org/v8/src/mips/ |
| assembler-mips.cc | 1305 void Assembler::srl(Register rd, Register rt, uint16_t sa) { function in class:v8::Assembler
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 562 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 357 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
476 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 930 enum BinaryOp { ADD, SHL, SRA, SRL, STRCONCAT, CONCAT, EQ };
[all...] |
