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  /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp 63 const MCSubtargetInfo &STI;
67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
R600MCCodeEmitter.cpp 43 const MCSubtargetInfo &STI;
48 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCCodeEmitter.cpp 40 const MCSubtargetInfo &STI;
45 const MCSubtargetInfo &sti, bool IsLittle) :
46 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {}
102 const MCSubtargetInfo &STI,
105 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
110 const MCSubtargetInfo &STI,
113 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
213 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
  /external/llvm/lib/Target/PowerPC/MCTargetDesc/
PPCMCCodeEmitter.cpp 35 const MCSubtargetInfo &STI;
40 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
42 : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
104 const MCSubtargetInfo &STI,
106 return new PPCMCCodeEmitter(MCII, STI, Ctx);
PPCMCTargetDesc.cpp 122 const MCSubtargetInfo &STI) {
123 bool isDarwin = Triple(STI.getTargetTriple()).isOSDarwin();
  /frameworks/compile/mclinker/lib/CodeGen/
MCLDTargetMachine.cpp 281 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
286 Context->getRegisterInfo(), STI);
291 MCE = getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
326 const MCSubtargetInfo &STI = getTM().getSubtarget<MCSubtargetInfo>();
328 getTarget().get()->createMCCodeEmitter(MII, MRI, STI, *Context);
  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 317 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
319 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
320 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
337 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
339 unsigned Size = STI.isABI_N64() ? 64 : 32;
340 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
341 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
342 const TargetRegisterClass *RC = STI.isABI_N64() ?
512 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
513 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu
    [all...]
  /external/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64MCTargetDesc.cpp 113 const MCSubtargetInfo &STI) {
115 return new AArch64InstPrinter(MAI, MII, MRI, STI);
AArch64AsmBackend.cpp 29 const MCSubtargetInfo* STI;
33 STI(AArch64_MC::createAArch64MCSubtargetInfo(TT, "", ""))
38 delete STI;
  /external/llvm/lib/Target/R600/MCTargetDesc/
SIMCCodeEmitter.cpp 51 const MCSubtargetInfo &sti, MCContext &ctx)
69 const MCSubtargetInfo &STI,
71 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
  /external/llvm/tools/llvm-mc/
Disassembler.cpp 156 MCSubtargetInfo &STI,
161 OwningPtr<const MCDisassembler> DisAsm(T.createMCDisassembler(STI));
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.h 79 const MCSubtargetInfo &STI,
  /external/llvm/lib/Target/XCore/MCTargetDesc/
XCoreMCTargetDesc.cpp 81 const MCSubtargetInfo &STI) {
  /external/clang/tools/driver/
cc1as_main.cpp 334 STI(TheTarget->createMCSubtargetInfo(Opts.Triple, Opts.CPU, FS));
340 *STI);
344 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
358 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
368 OwningPtr<MCTargetAsmParser> TAP(TheTarget->createMCAsmParser(*STI, *Parser));
  /external/llvm/lib/Target/SystemZ/Disassembler/
SystemZDisassembler.cpp 25 SystemZDisassembler(const MCSubtargetInfo &STI)
26 : MCDisassembler(STI) {}
40 const MCSubtargetInfo &STI) {
41 return new SystemZDisassembler(STI);
319 return decodeInstruction(Table, MI, Inst, Address, this, STI);
  /external/llvm/lib/Target/X86/Disassembler/
X86Disassembler.cpp 75 X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI,
78 : MCDisassembler(STI), MII(MII), fMode(mode) {}
717 const MCSubtargetInfo &STI) {
718 return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT,
723 const MCSubtargetInfo &STI) {
724 return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT,
  /external/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 383 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
384 isLikeA9 = STI->isLikeA9() || STI->isSwift();
385 isSwift = STI->isSwift();
ARMFrameLowering.cpp 46 if (STI.isTargetIOS())
194 if (STI.isTargetIOS()) {
281 if (STI.isTargetELF() && hasFP(MF))
446 unsigned TCOpcode = STI.isThumb() ?
447 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
460 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
463 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
598 if (!(Func)(Reg, STI.isTargetIOS())) continue;
669 if (!(Func)(Reg, STI.isTargetIOS())) continue;
675 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps())
    [all...]
  /external/llvm/tools/llvm-objdump/
MachODump.cpp 232 STI(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
233 OwningPtr<const MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
237 *MRI, *STI));
239 if (!InstrAnalysis || !AsmInfo || !STI || !DisAsm || !IP) {
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCTargetDesc.cpp 214 const MCSubtargetInfo &STI) {
216 return new ARMInstPrinter(MAI, MII, MRI, STI);
ARMAsmBackend.cpp 43 const MCSubtargetInfo* STI;
47 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
51 delete STI;
57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
  /external/llvm/lib/Target/NVPTX/InstPrinter/
NVPTXInstPrinter.cpp 32 const MCSubtargetInfo &STI)
34 setAvailableFeatures(STI.getFeatureBits());
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
R600MCCodeEmitter.cpp 43 const MCSubtargetInfo &STI;
48 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
  /external/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 34 XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
35 MCDisassembler(STI), RegInfo(Info) {}
764 Address, this, STI);
777 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
791 const MCSubtargetInfo &STI) {
792 return new XCoreDisassembler(STI, T.createMCRegInfo(""));
  /external/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
46 : MCDisassembler(STI), RegInfo(Info) {
230 this, STI);
811 const MCSubtargetInfo &STI) {
812 return new AArch64Disassembler(STI, T.createMCRegInfo(""));

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