| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.h | 52 unsigned &DstReg, unsigned &SubIdx) const;
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 112 /// SubIdx.
115 unsigned &SubIdx) const {
187 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
188 /// SubIdx.
191 unsigned DestReg, unsigned SubIdx,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 130 unsigned DestReg, unsigned SubIdx,
139 unsigned SubIdx, unsigned State,
|
| ARMBaseRegisterInfo.cpp | 388 unsigned DestReg, unsigned SubIdx, int Val,
399 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx,
79 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| ARMBaseInstrInfo.cpp | 746 unsigned SubIdx, unsigned State,
748 if (!SubIdx)
752 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
753 return MIB.addReg(Reg, State, SubIdx);
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 169 /// SubIdx.
172 unsigned &SubIdx) const;
191 unsigned DestReg, unsigned SubIdx,
|
| X86RegisterInfo.cpp | 128 unsigned SubIdx) const {
130 if (!Is64Bit && SubIdx == X86::sub_8bit) {
135 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
75 if (SubIdx)
76 setSubReg(SubIdx);
[all...] |
| MachineVerifier.cpp | 889 unsigned SubIdx = MO->getSubReg();
892 if (SubIdx) {
[all...] |
| TargetInstrInfo.cpp | 282 unsigned SubIdx,
286 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
|
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 411 unsigned SubIdx = (IsI64 ? Mips::sub_32 : Mips::sub_fpeven);
417 TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
420 DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
435 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
436 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
|
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 332 /// Reg so its sub-register of index SubIdx is Reg.
333 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 348 /// Reg must be a virtual register, SubIdx can be 0.
350 void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
|
| MachineInstr.h | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 714 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
717 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
[all...] |
| /external/llvm/utils/TableGen/ |
| AsmMatcherEmitter.cpp | [all...] |
