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  /external/oprofile/events/x86-64/hammer/
unit_masks 70 0x02 Page miss
90 0x01 Probe miss
118 0x04 GART miss
157 0x04 Read Block (Dcache load miss refill)
159 0x10 Read Block Modified (Dcache store miss refill)
180 0x04 The number of cycles spent in non-speculative phase (including cache miss penalty)
events 68 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
69 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
  /external/oprofile/events/mips/rm7000/
events 25 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
  /external/chromium/net/disk_cache/
stats.cc 43 "Open miss",
45 "Create miss",
320 int Stats::GetRatio(Counters hit, Counters miss) const {
325 ratio /= (GetCounter(hit) + GetCounter(miss));
  /external/chromium_org/net/disk_cache/
stats.cc 43 "Open miss",
45 "Create miss",
303 int Stats::GetRatio(Counters hit, Counters miss) const {
308 ratio /= (GetCounter(hit) + GetCounter(miss));
  /packages/apps/Email/src/com/android/email/provider/
ContentCache.java 107 // able to avoid a cache miss)
408 * included in baseProjection will always generate a cache miss
705 mStats.miss++;
740 // Basic cache miss (the item is not cached)
744 // A projection miss occurs when the item is cached, but not all requested columns are
754 private long miss = 0; field in class:ContentCache.Statistics
780 miss += cache.mStats.miss;
806 append(sb, "Miss time", missTimes / 1000000.0 / miss);
    [all...]
  /external/oprofile/events/x86-64/family10/
unit_masks 80 0x02 DCT0 Page miss
83 0x10 DCT1 Page miss
111 0x01 Probe miss
137 0x04 GART miss
140 0x20 DEV miss
176 0x04 Read Block (Dcache load miss refill)
178 0x10 Read Block Modified (Dcache store miss refill)
240 0x04 Cycles in non-speculative phase (including cache miss penalty)
241 0x08 Cache miss penalty in cycles
  /external/chromium_org/third_party/libxml/src/
gentest.py 945 for miss in missing_list:
946 lst.write("%s: %d :" % (miss[1], miss[0]))
948 for n in missing_types[miss[1]]:
  /external/chromium_org/v8/test/mjsunit/
keyed-call-ic.js 116 key = 'two'; // the name change should case a miss
126 key = 'two'; // the name change should case a miss
  /external/oprofile/events/mips/sb1/
events 42 event:0x3 counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
46 event:0xc counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
  /external/v8/test/mjsunit/
keyed-call-ic.js 116 key = 'two'; // the name change should case a miss
126 key = 'two'; // the name change should case a miss
array-store-and-grow.js 31 // by the runtime in the miss stub.
  /external/oprofile/events/i386/westmere/
events 17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event)
33 event:0x2e counters:0,1,2,3 um:longest_lat_cache minimum:100000 name:LONGEST_LAT_CACHE : Longest latency cache miss
46 event:0x85 counters:0,1,2,3 um:itlb_misses minimum:200000 name:ITLB_MISSES : ITLB miss
70 event:0xcb counters:0,1,2,3 um:mem_load_retired minimum:200000 name:MEM_LOAD_RETIRED : Retired loads that miss the DTLB (Precise Event)
  /external/oprofile/events/i386/atom/
unit_masks 44 0x02 misses Icache miss
98 0x02 l2_miss Retired loads that miss the L2 cache (precise event)
99 0x04 dtlb_miss Retired loads that miss the DTLB (precise event)
  /external/v8/src/x64/
code-stubs-x64.cc 4202 Label miss; local
5504 Label miss; local
5531 Label miss; local
5594 Label miss; local
5628 Label miss; local
5714 Label miss; local
5733 Label miss; local
5755 ExternalReference miss = local
    [all...]
  /external/v8/src/ia32/
macro-assembler-ia32.h 513 Label* miss);
517 void LoadFromNumberDictionary(Label* miss,
650 // function and jumps to the miss label if the fast checks fail. The
656 Label* miss,
    [all...]
code-stubs-ia32.cc 5141 Label miss; local
6511 Label miss; local
6540 Label miss; local
6612 Label miss; local
6648 Label miss; local
6737 Label miss; local
6757 Label miss; local
6780 ExternalReference miss = ExternalReference(IC_Utility(IC::kCompareIC_Miss), local
    [all...]
  /external/oprofile/events/x86-64/family11h/
events 68 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
69 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
  /external/chromium_org/v8/src/arm/
code-stubs-arm.h 466 Label* miss,
474 Label* miss,
  /external/chromium_org/v8/src/ia32/
code-stubs-ia32.h 232 Label* miss,
239 Label* miss,
  /external/chromium_org/v8/src/mips/
code-stubs-mips.h 482 Label* miss,
490 Label* miss,
  /external/chromium_org/v8/src/x64/
code-stubs-x64.h 223 Label* miss,
230 Label* miss,
  /external/oprofile/events/i386/nehalem/
unit_masks 25 0x02 walk_completed Counts number of completed page walks due to load miss in the STLB
29 0x80 large_walk_completed Counts number of completed large page walks due to load miss in the STLB
82 0x02 ld_miss Counts the number of loads that miss the L2 cache
85 0x08 rfo_miss Counts the number of store RFO requests that miss the L2 cache
88 0x20 ifetch_miss Counts number of instruction fetches that miss the L2 cache
93 0xAA miss Counts all L2 misses for both code and data
128 0x41 miss This event counts each cache miss condition for references to the last level cache
166 0x02 miss Counts number of hardware prefetch requests that miss the L1
    [all...]
  /external/oprofile/events/mips/rm9000/
events 24 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
  /external/v8/src/arm/
code-stubs-arm.cc 4092 Label miss; local
6540 Label miss; local
6564 Label miss; local
6624 Label miss; local
6662 Label miss; local
6740 Label miss; local
6759 Label miss; local
6781 ExternalReference miss = local
    [all...]

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