| /dalvik/vm/compiler/template/mips/ |
| TEMPLATE_SHL_LONG.S | 15 movn rRESULT1, rRESULT0, a2 # rhi<- rlo (if shift&0x20)
16 movn rRESULT0, zero, a2 # rlo<- 0 (if shift&0x20)
|
| TEMPLATE_SHR_LONG.S | 16 movn rRESULT0, rRESULT1, a2 # rlo<- rhi (if shift&0x20)
17 movn rRESULT1, a3, a2 # rhi<- sign(ahi) (if shift&0x20)
|
| TEMPLATE_USHR_LONG.S | 15 movn rRESULT0, rRESULT1, a2 # rlo<- rhi (if shift&0x20)
16 movn rRESULT1, zero, a2 # rhi<- 0 (if shift&0x20)
|
| TEMPLATE_STRING_INDEXOF.S | 43 movn a2, zero, t7
45 movn a2, t1, t7
|
| TEMPLATE_STRING_COMPARETO.S | 41 movn a2, t2, t7 # a2<- minCount
145 movn v0, rOBJ, t0 # overwrite return value if strings are equal
|
| /external/llvm/test/CodeGen/AArch64/ |
| movw-consts.ll | 52 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
56 ; CHECK: movn w0, #60875
62 ; CHECK: movn x0, #0
68 ; CHECK: movn x0, #60875, lsl #16
113 ; CHECK: movn {{w[0-9]+}}, #0
121 ; Mustn't MOVN w0 here.
122 ; CHECK: movn x0, #2
|
| variadic.ll | 25 ; CHECK: movn [[VR_OFFS:w[0-9]+]], #127
27 ; CHECK: movn [[GR_OFFS:w[0-9]+]], #55
55 ; CHECK: movn [[VR_OFFS:w[0-9]+]], #111
57 ; CHECK: movn [[GR_OFFS:w[0-9]+]], #39
97 ; CHECK: movn [[VR_OFFS:w[0-9]+]], #79
|
| /external/llvm/test/MC/AArch64/ |
| elf-reloc-movw.s | 17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
|
| tls-relocs.s | 7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
12 // CHECK: movn x2, #:dtprel_g2:var // encoding: [0x02'A',A,0xc0'A',0x92'A']
16 // CHECK: movn x4, #:dtprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A']
28 movn x6, #:dtprel_g1:var
30 movn w8, #:dtprel_g1:var
33 // CHECK: movn x6, #:dtprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A']
37 // CHECK: movn w8, #:dtprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A']
58 movn x12, #:dtprel_g0:var
60 movn w14, #:dtprel_g0:va
[all...] |
| /dalvik/vm/mterp/mips/ |
| OP_SHL_LONG.S | 27 movn v1, v0, a2 # rhi<- rlo (if shift&0x20)
28 movn v0, zero, a2 # rlo<- 0 (if shift&0x20)
|
| OP_SHL_LONG_2ADDR.S | 22 movn v1, v0, a2 # rhi<- rlo (if shift&0x20)
23 movn v0, zero, a2 # rlo<- 0 (if shift&0x20)
|
| OP_SHR_LONG.S | 27 movn v0, v1, a2 # rlo<- rhi (if shift&0x20)
28 movn v1, a3, a2 # rhi<- sign(ahi) (if shift&0x20)
|
| OP_SHR_LONG_2ADDR.S | 22 movn v0, v1, a2 # rlo<- rhi (if shift&0x20)
23 movn v1, a3, a2 # rhi<- sign(ahi) (if shift&0x20)
|
| OP_USHR_LONG.S | 26 movn v0, v1, a2 # rlo<- rhi (if shift&0x20)
27 movn v1, zero, a2 # rhi<- 0 (if shift&0x20)
|
| OP_USHR_LONG_2ADDR.S | 21 movn v0, v1, a2 # rlo<- rhi (if shift&0x20)
22 movn v1, zero, a2 # rhi<- 0 (if shift&0x20)
|
| /external/llvm/test/CodeGen/Mips/ |
| zeroreg.ll | 7 ; CHECK: movn ${{[0-9]+}}, $zero
|
| cmov.ll | 10 ; O32: movn $[[R0]], $[[R1]], ${{[0-9]+}}
13 ; N64: movn $[[R0]], $[[R1]], ${{[0-9]+}}
28 ; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
32 ; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
|
| /external/llvm/lib/Target/Mips/ |
| MipsCondMov.td | 118 def MOVN_I_I : CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
122 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd,
124 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd,
126 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd,
137 def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32RegsOpnd, IIFmove>,
141 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32RegsOpnd, IIFmove>,
147 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64RegsOpnd, IIFmove>,
156 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64RegsOpnd, IIFmove>,
158 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64RegsOpnd,
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.c | 208 // movn.s fd, fs, rt
229 // movn.d fd, fs, rt
451 printf("MOVN.S\n");
452 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 0, 0, f0, f2, t3);
453 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 4, 1, f0, f2, t3);
454 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 8, 0xffff, f0, f2, t3);
455 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 12, -1, f0, f2, t3);
456 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 16, 5, f0, f2, t3);
457 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 20, 0, f0, f2, t3);
458 TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 24, 0, f0, f2, t3)
[all...] |
| MoveIns.stdout.exp | 192 MOVN.S
193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db000
[all...] |
| MoveIns.stdout.exp-BE | 192 MOVN.S
193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db000
[all...] |
| /external/kernel-headers/original/asm-mips/ |
| asm.h | 166 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
169 #define MOVN(rd, rs, rt) \
185 #define MOVN(rd, rs, rt) \
202 #define MOVN(rd, rs, rt) \
203 movn rd, rs, rt
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips.cc | 381 COMPARE(movn(a0, a1, a2),
382 "00a6200b movn a0, a1, a2");
383 COMPARE(movn(s0, s1, s2),
384 "0232800b movn s0, s1, s2");
385 COMPARE(movn(t2, t3, t4),
386 "016c500b movn t2, t3, t4");
387 COMPARE(movn(v0, v1, a2),
388 "0066100b movn v0, v1, a2");
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 391 COMPARE(movn(a0, a1, a2),
392 "00a6200b movn a0, a1, a2");
393 COMPARE(movn(s0, s1, s2),
394 "0232800b movn s0, s1, s2");
395 COMPARE(movn(t2, t3, t4),
396 "016c500b movn t2, t3, t4");
397 COMPARE(movn(v0, v1, a2),
398 "0066100b movn v0, v1, a2");
|
| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 79 DBG movn $v0,$t8,$at
81 DBG movn $v1,$t8,$at
166 DBG movn $v0,$t8,$at
168 DBG movn $v1,$t8,$at
|
