| /external/llvm/test/CodeGen/Mips/ |
| buildpairextractelementf64.ll | 7 ; CHECK: mtc1
8 ; CHECK: mtc1
|
| 2008-08-04-Bitconvert.ll | 5 ; CHECK: mtc1
|
| constantfp0.ll | 5 ; CHECK: mtc1 $zero, $f[[R0:[0-9]+]]
|
| int-to-float-conversion.ll | 8 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
18 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
21 ; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
|
| fabs.ll | 13 ; 32: mtc1 $[[AND]], $f0
16 ; 32R2: mtc1 $[[INS]], $f0
32 ; 32: mtc1 $[[AND]], $f1
35 ; 32R2: mtc1 $[[INS]], $f1
|
| fcopysign.ll | 15 ; 32: mtc1 $[[OR]], $f1
19 ; 32R2: mtc1 $[[INS]], $f1
48 ; 32: mtc1 $[[OR]], $f0
52 ; 32R2: mtc1 $[[INS]], $f0
|
| hf16call32.ll | [all...] |
| fcopysign-f32-f64.ll | 18 ; 64: mtc1 $[[OR]], $f0
22 ; 64R2: mtc1 $[[INS]], $f0
|
| selectcc.ll | 23 ; SOURCE-SCHED: mtc1
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.c | 62 // mtc1 rt, fs
145 "mtc1 $t0, $f0\n\t" \
146 "mtc1 $t1, $f2\n\t" \
167 "mtc1 $t0, $f0\n\t" \
168 "mtc1 $t1, $f2\n\t" \
191 "mtc1 $t0, $f0\n\t" \
192 "mtc1 $t1, $f2\n\t" \
217 "mtc1 $0, $" #FD "\n\t" \
238 "mtc1 $0, $" #FD "\n\t" \
239 "mtc1 $0, $" #FD + 1"\n\t"
[all...] |
| MoveIns.stdout.exp | 29 MTC1
30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
38 mtc1 $v1, $f8 :: fs nan, rt 0xfffffff
[all...] |
| MoveIns.stdout.exp-BE | 29 MTC1
30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
38 mtc1 $v1, $f8 :: fs nan, rt 0xfffffff
[all...] |
| round.c | 109 "mtc1 %1, $f0\n\t" \
117 "mtc1 %1, $f0\n\t" \
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 95 /// MTC1 F4, A5
99 /// instruction between MTC1 and CVT_D32_W.
|
| MipsSEInstrInfo.cpp | 122 Opc = Mips::MTC1;
255 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
258 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
264 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
445 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
449 // mtc1 Lo, $fp
450 // mtc1 Hi, $fp + 1
|
| MipsInstrFPU.td | 339 def MTC1 : MTC1_FT<"mtc1", FGR32RegsOpnd, GPR32Opnd, IIFmoveC1, bitconvert>,
543 // This pseudo instr gets expanded into 2 mtc1 instrs after register
569 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
570 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
|
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-mips.cc | 293 __ mtc1(t0, f14);
371 __ mtc1(t0, f6);
372 __ mtc1(t1, f7);
373 __ mtc1(t2, f4);
374 __ mtc1(t3, f5);
437 __ mtc1(t0, f12);
442 __ mtc1(t1, f14);
798 __ mtc1(t0, f8); // f8 has LS 32-bits.
799 __ mtc1(t1, f9); // f9 has MS 32-bits.
[all...] |
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 303 __ mtc1(t0, f14);
372 __ mtc1(t0, f6);
373 __ mtc1(t1, f7);
374 __ mtc1(t2, f4);
375 __ mtc1(t3, f5);
441 __ mtc1(t0, f12);
446 __ mtc1(t1, f14);
804 __ mtc1(t0, f8); // f8 has LS 32-bits.
805 __ mtc1(t1, f9); // f9 has MS 32-bits.
[all...] |
| /development/ndk/sources/android/libportable/arch-mips/ |
| _setjmp.S | 56 mtc1 t1, FPR ; \
|
| setjmp.S | 56 mtc1 t1, FPR ; \
|
| /bionic/libc/arch-mips/bionic/ |
| _setjmp.S | 55 mtc1 t1, FPR ; \
|
| setjmp.S | 56 mtc1 t1, FPR ; \
|
| /external/chromium_org/v8/src/mips/ |
| macro-assembler-mips.cc | 1033 mtc1(at, fd);
1046 mtc1(at, FPURegister::from_code(scratch.code() + 1));
1047 mtc1(zero_reg, scratch);
1059 mtc1(t8, fd);
1067 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1078 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1089 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1100 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1115 mtc1(at, FPURegister::from_code(scratch.code() + 1));
1116 mtc1(zero_reg, scratch)
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 999 mtc1(at, fd);
1012 mtc1(at, FPURegister::from_code(scratch.code() + 1));
1013 mtc1(zero_reg, scratch);
1025 mtc1(t8, fd);
1032 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1042 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1053 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1064 mtc1(t8, FPURegister::from_code(fs.code() + 1));
1079 mtc1(at, FPURegister::from_code(scratch.code() + 1));
1080 mtc1(zero_reg, scratch)
[all...] |
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 63 /* note the operands are swapped for the mtc1 instr */
875 /* note the operands are swapped for the mtc1 instr */
|
