| /hardware/qcom/display/msm8974/liboverlay/ |
| overlayWriteback.cpp | 75 //=========== class Writeback =================================================
76 Writeback::Writeback() : mXres(0), mYres(0), mOpFmt(-1) {
85 Writeback::~Writeback() {
92 bool Writeback::startSession() {
100 bool Writeback::stopSession() {
113 bool Writeback::configureDpyInfo(int xres, int yres) {
137 bool Writeback::configureMemory(uint32_t size, bool isSecure) {
145 bool Writeback::queueBuffer(int opFd, uint32_t opOffset)
[all...] |
| overlayWriteback.h | 61 class Writeback {
63 ~Writeback();
67 * This class will do writeback memory management.
68 * This class will call display-commit on writeback mixer.
72 * Client must do writeback memory management.
73 * Client must not call display-commit on writeback mixer.
77 * Client must do writeback memory management.
84 /* Subject to GC if writeback isnt used for a drawing round.
91 static Writeback* getInstance();
100 explicit Writeback();
[all...] |
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/ |
| shelve.py | 43 argument writeback=True in the call to shelve.open. When you use:
44 d = shelve.open(filename, writeback=True)
49 However, using keyword argument writeback=True may consume vast amount
92 def __init__(self, dict, protocol=None, writeback=False):
97 self.writeback = writeback
123 if self.writeback:
128 if self.writeback:
156 if not hasattr(self, 'writeback'):
162 if self.writeback and self.cache
[all...] |
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/ |
| shelve.py | 43 argument writeback=True in the call to shelve.open. When you use:
44 d = shelve.open(filename, writeback=True)
49 However, using keyword argument writeback=True may consume vast amount
92 def __init__(self, dict, protocol=None, writeback=False):
97 self.writeback = writeback
123 if self.writeback:
128 if self.writeback:
156 if not hasattr(self, 'writeback'):
162 if self.writeback and self.cache
[all...] |
| /external/kernel-headers/original/asm-mips/ |
| cachectl.h | 15 #define DCACHE (1<<1) /* writeback and flush data cache */
|
| sysmips.h | 20 #define FLUSH_CACHE 3 /* writeback and invalidate caches */
|
| /hardware/qcom/display/msm8974/libhwcomposer/ |
| hwc_ad.cpp | 43 //Opens writeback framebuffer and returns fd.
52 //Opening writeback fb first time would create ad node if the device
60 ALOGD_IF(DEBUG, "%s: No writeback available", __func__);
178 overlay::Writeback *wb = overlay::Writeback::getInstance();
244 overlay::Writeback *wb = overlay::Writeback::getInstance();
253 overlay::Writeback *wb = overlay::Writeback::getInstance();
258 overlay::Writeback *wb = overlay::Writeback::getInstance()
[all...] |
| hwc.cpp | 230 ctx->dpyAttr[dpy].fd = Writeback::getInstance()->getFbFd();
232 Writeback::getInstance()->configureDpyInfo(ohnd->width, ohnd->height);
254 overlay::Writeback::configBegin();
285 overlay::Writeback::configDone();
334 overlay::Writeback::clear();
514 Writeback::getInstance()->setOutputFormat(
531 Writeback::getInstance()->queueBuffer(ohnd->fd, ohnd->offset);
683 if(Writeback::getDump(ovDump, 1024)) {
|
| hwc_uevents.cpp | 121 //WriteBack module. If HDMI attempts to open fb1, the driver
123 //fail, since Layer Mixer#0 is still connected to WriteBack.
|
| /external/clang/lib/CodeGen/ |
| CGCall.h | 59 struct Writeback {
67 /// A value to "use" after the writeback, or null.
91 Writeback writeback; local
92 writeback.Source = srcLV;
93 writeback.Temporary = temporary;
94 writeback.ToUse = toUse;
95 Writebacks.push_back(writeback);
100 typedef SmallVectorImpl<Writeback>::const_iterator writeback_iterator;
117 SmallVector<Writeback, 1> Writebacks
[all...] |
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/test/ |
| test_shelve.py | 15 s = shelve.Shelf(d1, protocol=2, writeback=False)
75 s = shelve.Shelf(d1, protocol=2, writeback=False)
83 s = shelve.Shelf(d2, protocol=2, writeback=True)
96 s = shelve.Shelf(d, writeback=True)
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/test/ |
| test_shelve.py | 15 s = shelve.Shelf(d1, protocol=2, writeback=False)
75 s = shelve.Shelf(d1, protocol=2, writeback=False)
83 s = shelve.Shelf(d2, protocol=2, writeback=True)
96 s = shelve.Shelf(d, writeback=True)
|
| /external/oprofile/events/arm/armv6/ |
| events.h | 25 "data cache writeback, 1 event for every half cacheline"},
|
| events | 14 event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
| /external/clang/test/SemaObjCXX/ |
| arc-overloading.mm | 57 // Writeback conversion
72 // Writeback conversion vs. no conversion
88 // Writeback conversion vs. other conversion.
|
| /external/llvm/test/MC/ARM/ |
| thumb-diagnostics.s | 41 @ Invalid writeback and register lists for LDM
48 @ CHECK-ERRORS: error: writeback operator '!' expected
51 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
56 @ Invalid writeback and register lists for PUSH/POP
67 @ Invalid writeback and register lists for STM
|
| /art/compiler/utils/arm/ |
| assembler_arm.h | 148 DA_W = (0|0|1) << 21, // decrement after with writeback to base
149 IA_W = (0|4|1) << 21, // increment after with writeback to base
150 DB_W = (8|0|1) << 21, // decrement before with writeback to base
151 IB_W = (8|4|1) << 21 // increment before with writeback to base
160 Offset = (8|4|0) << 21, // offset (w/o writeback to base)
161 PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback
162 PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback
163 NegOffset = (8|0|0) << 21, // negative offset (w/o writeback to base)
164 NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback
165 NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 191 W = 1 << 21, // Writeback base register (or leave unchanged).
285 Offset = (8|4|0) << 21, // Offset (without writeback to base).
286 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback.
287 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback.
288 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base).
289 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback.
290 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback.
301 da_w = (0|0|1) << 21, // Decrement after with writeback to base.
302 ia_w = (0|4|1) << 21, // Increment after with writeback to base.
303 db_w = (8|0|1) << 21, // Decrement before with writeback to base
[all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 229 W = 1 << 21, // Writeback base register (or leave unchanged).
320 Offset = (8|4|0) << 21, // Offset (without writeback to base).
321 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback.
322 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback.
323 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base).
324 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback.
325 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback.
336 da_w = (0|0|1) << 21, // Decrement after with writeback to base.
337 ia_w = (0|4|1) << 21, // Increment after with writeback to base.
338 db_w = (8|0|1) << 21, // Decrement before with writeback to base
[all...] |
| /packages/inputmethods/PinyinIME/src/com/android/inputmethod/pinyin/ |
| Settings.java | 54 public static void writeBack() {
|
| SettingsActivity.java | 88 Settings.writeBack();
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 263 amode.writeback = W;
285 // amode.writeback = W;
321 LOG_ALWAYS_FATAL_IF(W, "reg_pre writeback not yet implemented");
776 amode.writeback = 0;
783 if (amode.writeback) { // OPTIONAL writeback on pre-index mode
810 amode.writeback = 0;
814 if (amode.writeback) { // OPTIONAL writeback on pre-index mode
839 amode.writeback = 0
[all...] |
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_STRING_COMPARETO.S | 47 * mode with base writeback.
|
| /external/kernel-headers/original/asm-arm/ |
| page.h | 45 * v4wb - ARMv4 with writeback cache, without minicache
|
| /external/oprofile/events/arm/xscale1/ |
| events | 15 event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
|
