Lines Matching full:vector
124 // Vector opcodes:
125 // TypeSize is an encoded field giving the element type and the vector size.
126 // It is encoded as OpSize << 16 | (number of bits in vector)
129 // backend that supports Vector operations. Backends are permitted to support only
130 // certain vector register sizes.
135 // @brief MIR to move constant data to a vector register
147 // @brief Packed multiply of units in two vector registers: vB = vB .* vC using vA to know the type of the vector.
153 // @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector.
159 // @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector.
165 // @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector.
171 // @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector.
177 // @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector.
183 // @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector.
189 // @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector.
195 // @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector.
203 // vA: destination and source VR (not vector register)
204 // vB: source (vector register)
209 // vA: destination VR (not vector register)
210 // vB: source (vector register)
212 // arg[0]: The index to use for extraction from vector register (which packed element)
215 // @brief Create a vector value, with all TypeSize values equal to vC
216 // vA: destination vector register
217 // vB: source VR (not vector register)
221 // @brief Reserve N vector registers (named 0..N-1)
223 // @note: The backend may choose to map vector numbers used in vector opcodes.
227 // @brief Free Reserved vector registers
228 // @note: All currently reserved vector registers are returned to the temporary pool.
