Lines Matching refs:LIR
73 LIR* CheckSuspendUsingLoad() OVERRIDE;
75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest,
79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
81 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale)
83 LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE;
84 LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE;
85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile)
89 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
91 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE;
93 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
94 int offset, int check_value, LIR* target, LIR** compare) OVERRIDE;
125 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
126 void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
130 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE;
133 size_t GetInsnSize(LIR* lir) OVERRIDE;
134 bool IsUnconditionalBranch(LIR* lir) OVERRIDE;
204 LIR* OpUnconditionalBranch(LIR* target) OVERRIDE;
205 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
206 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
207 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
208 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
209 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
210 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
211 void OpEndIT(LIR* it) OVERRIDE;
212 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
213 LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE;
214 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
216 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE;
217 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
218 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
219 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
220 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
221 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
222 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
223 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
224 LIR* OpTestSuspend(LIR* target) OVERRIDE;
225 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
226 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
237 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel,
244 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel,
258 size_t GetInstructionOffset(LIR* lir) OVERRIDE;
260 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
337 LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value);
338 LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value);
339 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
340 LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
345 size_t GetLoadStoreSize(LIR* lir);
350 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);
353 uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
364 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value);
365 LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value);
367 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
368 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
372 LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
374 LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
379 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
380 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
