Lines Matching full:is_div
403 bool Arm64Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,
413 if (!is_div) {
447 bool Arm64Mir2Lir::SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div,
457 if (!is_div) {
514 bool Arm64Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div,
516 return HandleEasyDivRem64(dalvik_opcode, is_div, rl_src, rl_dest, static_cast<int>(lit));
521 bool Arm64Mir2Lir::HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div,
531 return SmallLiteralDivRem64(dalvik_opcode, is_div, rl_src, rl_dest, lit);
533 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, static_cast<int32_t>(lit));
555 if (is_div) {
592 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) {
597 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) {
605 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div);
612 RegLocation rl_src2, bool is_div, bool check_zero) {
618 bool is_div) {
622 if (is_div) {
1004 RegLocation rl_src1, RegLocation rl_src2, bool is_div) {
1008 if (HandleEasyDivRem64(opcode, is_div, rl_src1, rl_dest, lit)) {
1017 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, is_div);
1070 GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true);
1074 GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false);
