Lines Matching refs:rl_src1
49 void Arm64Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
52 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
56 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
64 RegLocation rl_src1, RegLocation rl_shift) {
83 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
85 OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg));
215 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0);
221 if (rl_src1.is_const) {
222 std::swap(rl_src1, rl_src2);
226 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
229 // TODO: Optimize for rl_src1.is_const? (Does happen in the boot image at the moment.)
234 OpCmpImmBranch(ccode, rl_src1.reg, 0, taken);
235 OpCmpImmBranch(NegateComparison(ccode), rl_src1.reg, 0, not_taken);
242 OpRegImm64(kOpCmp, rl_src1.reg, val);
250 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
592 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) {
611 RegLocation Arm64Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
660 RegLocation rl_src1 = info->args[0];
662 rl_src1 = (is_long) ? LoadValueWide(rl_src1, kCoreReg) : LoadValue(rl_src1, kCoreReg);
666 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
668 rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), (is_min) ? kArmCondLt : kArmCondGt);
1004 RegLocation rl_src1, RegLocation rl_src2, bool is_div) {
1008 if (HandleEasyDivRem64(opcode, is_div, rl_src1, rl_dest, lit)) {
1014 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
1017 rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, is_div);
1021 void Arm64Mir2Lir::GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1,
1025 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
1028 OpRegRegRegShift(op, rl_result.reg, rl_src1.reg, rl_src2.reg, ENCODE_NO_SHIFT);
1051 RegLocation rl_src1, RegLocation rl_src2) {
1058 GenLongOp(kOpAdd, rl_dest, rl_src1, rl_src2);
1062 GenLongOp(kOpSub, rl_dest, rl_src1, rl_src2);
1066 GenLongOp(kOpMul, rl_dest, rl_src1, rl_src2);
1070 GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true);
1074 GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false);
1078 GenLongOp(kOpAnd, rl_dest, rl_src1, rl_src2);
1082 GenLongOp(kOpOr, rl_dest, rl_src1, rl_src2);
1086 GenLongOp(kOpXor, rl_dest, rl_src1, rl_src2);
1328 RegLocation rl_src1, RegLocation rl_src2) {
1357 return GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
1362 DCHECK(rl_src1.is_const);
1363 std::swap(rl_src1, rl_src2);
1369 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
1371 OpRegRegImm64(op, rl_result.reg, rl_src1.reg, val);
