Lines Matching refs:r_src2
566 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) {
568 CHECK_EQ(r_dest_src1.Is64Bit(), r_src2.Is64Bit());
593 return NewLIR2(kA64Rev2rr | wide, r_dest_src1.GetReg(), r_src2.GetReg());
597 NewLIR2(kA64Rev162rr | wide, r_dest_src1.GetReg(), r_src2.GetReg());
605 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 7);
609 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15);
614 return NewLIR4(kA64Ubfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15);
616 return OpRegRegRegShift(op, r_dest_src1, r_dest_src1, r_src2, shift);
622 return NewLIR2(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg());
626 return NewLIR3(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg(), shift);
634 LIR* Arm64Mir2Lir::OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
649 return OpRegRegRegExtend(op, r_dest_src1, r_dest_src1, r_src2, ext, amount);
660 return NewLIR3(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg(),
669 LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
674 return OpRegRegExtend(op, r_dest_src1, r_src2, kA64Uxtx, 0);
676 return OpRegRegShift(op, r_dest_src1, r_src2, ENCODE_NO_SHIFT);
696 RegStorage r_src2, int shift) {
752 CHECK_EQ(r_dest.Is64Bit(), r_src2.Is64Bit());
755 return NewLIR4(widened_opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg(), shift);
759 return NewLIR3(widened_opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg());
764 RegStorage r_src2, A64RegExtEncodings ext, uint8_t amount) {
785 if (!r_src2.Is64Bit()) {
786 r_src2 = As64BitReg(r_src2);
790 CHECK(!r_src2.Is64Bit());
797 return NewLIR4(widened_opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg(),
801 LIR* Arm64Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {
802 return OpRegRegRegShift(op, r_dest, r_src1, r_src2, ENCODE_NO_SHIFT);
