Lines Matching refs:reg
41 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
42 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0
44 NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg());
45 NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg());
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg,
108 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
109 NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg.GetReg(), reg.GetReg());
111 if (reg.Is64Bit()) {
112 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp64RI8 : kX86Cmp64RI, reg.GetReg(), check_value);
114 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value);
124 // If src or dest is a pair, we'll be using low reg.
289 LoadConstantNoClobber(rl_result.reg, true_val);
317 (rl_src.location == kLocPhysReg && rl_src.reg.GetRegNum() == rl_result.reg.GetRegNum());
323 OpRegReg(kOpXor, rl_result.reg, rl_result.reg);
327 OpRegImm(kOpCmp, rl_src.reg, 0);
331 OpRegImm(kOpMov, rl_result.reg, false_val);
340 OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg);
369 OpRegImm(kOpCmp, rl_src.reg, 0);
371 if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) {
372 OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg);
373 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) {
374 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
376 OpRegCopy(rl_result.reg, rl_false.reg);
377 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
405 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
458 NewLIR2(kX86Test64RR, rl_src1.reg.GetReg(), rl_src1.reg.GetReg());
460 OpRegImm(kOpCmp, rl_src1.reg, val_lo);
464 OpRegReg(kOpCmp, rl_src1.reg, tmp);
474 RegStorage low_reg = rl_src1.reg.GetLow();
475 RegStorage high_reg = rl_src1.reg.GetHigh();
483 Clobber(rl_src1.reg);
497 Clobber(rl_src1.reg);
512 Clobber(rl_src1.reg);
610 LoadValueDirectFixed(rl_src, rl_result.reg);
613 LoadConstantNoClobber(rl_result.reg, 0);
618 LoadValueDirectFixed(rl_src, rl_result.reg);
619 OpRegImm(kOpCmp, rl_result.reg, 0x80000000);
623 NewLIR1(kX86Neg32R, rl_result.reg.GetReg());
629 LoadConstantNoClobber(rl_result.reg, 0);
635 if (IsSameReg(rl_result.reg, rl_src.reg)) {
637 rl_result.reg.SetReg(rs_temp.GetReg());
639 NewLIR3(kX86Lea32RM, rl_result.reg.GetReg(), rl_src.reg.GetReg(), std::abs(imm) - 1);
640 NewLIR2(kX86Test32RR, rl_src.reg.GetReg(), rl_src.reg.GetReg());
641 OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg);
643 OpRegImm(kOpAsr, rl_result.reg, shift_amount);
645 OpReg(kOpNeg, rl_result.reg);
687 numerator_reg = rl_src.reg;
740 rl_result.reg.SetReg(r0);
797 rl_result.reg.SetReg(r2);
823 if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) {
828 OpRegCopy(rl_result.reg, rl_src1.reg);
832 if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) {
834 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
838 OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg);
861 LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile);
890 if (rl_src_value.location == kLocPhysReg && !IsByteRegister(rl_src_value.reg)) {
892 OpRegCopy(temp, rl_src_value.reg);
893 rl_value.reg = temp;
901 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile);
919 static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) {
920 return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home);
946 NewLIR5(kX86LockCmpxchg64AR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0,
947 rl_new_value.reg.GetReg());
970 // If obj/offset is in a reg, use that reg. Otherwise, use the empty reg.
1032 MarkGCCard(rl_new_value.reg, rl_object.reg);
1043 NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0,
1044 rl_new_value.reg.GetReg());
1058 RegStorage result_reg = rl_result.reg;
1065 NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), result_reg.GetReg());
1073 LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) {
1079 LoadValueDirectWideFixed(rl_method, reg);
1081 LoadValueDirectFixed(rl_method, reg);
1090 LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256,
1112 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit);
1113 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg);
1116 OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit);
1120 void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) {
1122 DCHECK(reg.Is64Bit());
1124 NewLIR2(kX86Cmp64RI8, reg.GetReg(), 0);
1126 DCHECK(reg.IsPair());
1131 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh());
1236 LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) {
1237 OpRegImm(kOpSub, reg, 1);
1376 OpRegReg(kOpXor, rl_result.reg, rl_result.reg);
1378 OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow());
1379 OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh());
1413 GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo);
1414 GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi);
1428 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg());
1466 if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() &&
1467 rl_result.reg.GetReg() == rl_src2.reg.GetReg()) {
1468 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_result.reg.GetReg());
1469 } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() &&
1470 rl_result.reg.GetReg() == rl_src2.reg.GetReg()) {
1471 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg());
1472 } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() &&
1473 rl_result.reg.GetReg() != rl_src2.reg.GetReg()) {
1474 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg());
1476 OpRegCopy(rl_result.reg, rl_src1.reg);
1477 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg());
1499 NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg());
1509 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg());
1523 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg());
1531 NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg());
1542 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg());
1557 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg());
1565 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg());
1590 NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg());
1593 if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) {
1596 OpRegCopy(temp_reg, rl_dest.reg);
1597 rl_src.reg.SetHighReg(temp_reg.GetReg());
1599 NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg());
1602 NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg());
1603 FreeTemp(rl_src.reg); // ???
1615 LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(),
1621 lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET);
1651 cu_->target64 ? rl_src.reg.GetReg() : rl_src.reg.GetLowReg());
1658 lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg());
1664 FreeTemp(rl_src.reg);
1711 if (IsTemp(rl_src1.reg)) {
1716 if (!IsTemp(rl_src2.reg)) {
1730 if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) {
1735 if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) {
1758 OpRegCopy(rl_result.reg, rl_src.reg);
1759 OpReg(kOpNot, rl_result.reg);
1777 LoadConstantWide(rl_result.reg, 0);
1786 OpRegCopy(rl_result.reg, rl_src.reg);
1790 OpRegReg(kOpCmp, rl_src.reg, rs_temp);
1794 OpReg(kOpNeg, rl_result.reg);
1802 LoadConstantWide(rl_result.reg, 0);
1809 if (IsSameReg(rl_result.reg, rl_src.reg)) {
1811 rl_result.reg.SetReg(rs_temp.GetReg());
1813 LoadConstantWide(rl_result.reg, std::abs(imm) - 1);
1814 OpRegReg(kOpAdd, rl_result.reg, rl_src.reg);
1815 NewLIR2(kX86Test64RR, rl_src.reg.GetReg(), rl_src.reg.GetReg());
1816 OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg);
1818 OpRegImm(kOpAsr, rl_result.reg, shift_amount);
1820 OpReg(kOpNeg, rl_result.reg);
1862 numerator_reg = rl_src.reg;
1926 OpRegCopyWide(rl_result.reg, rs_r0q);
1929 OpRegCopyWide(rl_result.reg, rs_r2q);
1992 rl_result.reg.SetReg(r2q);
2003 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg);
2007 ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) {
2010 OpRegCopy(temp_reg, rl_result.reg);
2011 rl_result.reg.SetHighReg(temp_reg.GetReg());
2013 OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow
2014 OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF
2015 OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh
2082 rl_index.reg = RegStorage::InvalidReg();
2086 GenNullCheck(rl_array.reg, opt_flags);
2090 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset);
2092 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset);
2096 LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size);
2130 rl_index.reg = RegStorage::InvalidReg();
2134 GenNullCheck(rl_array.reg, opt_flags);
2138 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset);
2140 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset);
2148 // If the src reg can't be byte accessed, move it to a temp first.
2149 if ((size == kSignedByte || size == kUnsignedByte) && !IsByteRegister(rl_src.reg)) {
2151 OpRegCopy(temp, rl_src.reg);
2152 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size);
2154 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size);
2159 FreeTemp(rl_index.reg);
2161 MarkGCCard(rl_src.reg, rl_array.reg);
2186 OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount);
2193 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow());
2194 LoadConstant(rl_result.reg.GetLow(), 0);
2196 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow());
2197 NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32);
2198 LoadConstant(rl_result.reg.GetLow(), 0);
2200 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow());
2201 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
2202 NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(),
2204 NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount);
2210 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
2211 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
2212 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31);
2214 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
2215 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
2216 NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32);
2217 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31);
2219 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow());
2220 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
2221 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(),
2223 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount);
2229 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
2230 LoadConstant(rl_result.reg.GetHigh(), 0);
2232 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh());
2233 NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32);
2234 LoadConstant(rl_result.reg.GetHigh(), 0);
2236 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow());
2237 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh());
2238 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(),
2240 NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount);
2399 DCHECK(in_mem || !loc.reg.IsFloat());
2496 DCHECK(!rl_result.reg.IsFloat());
2499 NewLIR2(x86op, rl_result.reg.GetReg(), val);
2537 DCHECK(!rl_result.reg.IsFloat());
2541 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo);
2545 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi);
2562 rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) {
2564 OpRegCopy(rl_dest.reg, rl_src1.reg);
2565 NewLIR2(x86op, rl_dest.reg.GetReg(), val);
2575 NewLIR2(x86op, rl_result.reg.GetReg(), val);
2588 rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() &&
2589 rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) {
2592 NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo);
2596 NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi);
2610 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo);
2614 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi);
2627 RegStorage result_reg = rl_result.reg;
2630 RegStorage object_32reg = object.reg.Is64Bit() ? As32BitReg(object.reg) : object.reg;
2637 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL);
2654 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(),
2657 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(),
2675 OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value());
2684 OpRegCopy(rl_result.reg, result_reg);
2801 // If we generate any memory access below, it will reference a dalvik reg.
2808 OpRegReg(op, rl_result.reg, rl_lhs.reg);
2823 } else if (!rl_result.reg.IsFloat()) {
2825 OpRegReg(op, rl_result.reg, t_reg);
2834 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg);
2842 // Ensure res is in a core reg
2847 OpRegMem(op, rl_result.reg, rl_rhs);
2850 } else if (!rl_rhs.reg.IsFloat()) {
2851 OpRegReg(op, rl_result.reg, rl_rhs.reg);
2858 // in this case rl_dest is in reg after LoadValue while
2863 OpMemReg(op, rl_result, rl_rhs.reg.GetReg());
2865 } else if (!rl_result.reg.IsFloat()) {
2867 OpRegReg(op, rl_result.reg, rl_rhs.reg);
2873 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
2876 // Try to use reg/memory instructions.
2885 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
2898 OpRegCopy(rl_result.reg, rl_lhs.reg);
2901 LoadValueDirect(rl_lhs, rl_result.reg);
2903 OpRegMem(op, rl_result.reg, rl_rhs);
2909 OpRegCopy(rl_result.reg, rl_rhs.reg);
2910 OpRegMem(op, rl_result.reg, rl_lhs);
2916 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
2923 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg);
2934 if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) {
2937 if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) {
2953 NewLIR2(kX86MovsxdRR, rl_result.reg.GetReg(), rl_src.reg.GetReg());
2957 LIR *m = NewLIR3(kX86MovsxdRM, rl_result.reg.GetReg(), rs_rX86_SP.GetReg(),
3009 } else if (!rl_result.reg.IsFloat()) {
3011 OpRegReg(op, rl_result.reg, t_reg);
3018 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg);
