Lines Matching refs:rl_src1
34 void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
37 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
41 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
56 LoadValueDirectWideFixed(rl_src1, r_tmp1);
386 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0);
390 if (rl_src1.is_const) {
391 std::swap(rl_src1, rl_src2);
397 GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode);
402 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
405 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
414 LoadValueDirectWideFixed(rl_src1, r_tmp1);
447 void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
452 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
458 NewLIR2(kX86Test64RR, rl_src1.reg.GetReg(), rl_src1.reg.GetReg());
460 OpRegImm(kOpCmp, rl_src1.reg, val_lo);
464 OpRegReg(kOpCmp, rl_src1.reg, tmp);
472 rl_src1 = ForceTempWide(rl_src1);
474 RegStorage low_reg = rl_src1.reg.GetLow();
475 RegStorage high_reg = rl_src1.reg.GetHigh();
483 Clobber(rl_src1.reg);
497 Clobber(rl_src1.reg);
512 Clobber(rl_src1.reg);
753 RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
760 LoadValueDirectFixed(rl_src1, rs_r0);
810 RegLocation rl_src1 = info->args[0];
812 rl_src1 = (is_long) ? LoadValueWide(rl_src1, kCoreReg) : LoadValue(rl_src1, kCoreReg);
824 std::swap(rl_src1, rl_src2);
828 OpRegCopy(rl_result.reg, rl_src1.reg);
832 if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) {
834 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
1295 void X86Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
1305 Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
1321 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true);
1326 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false);
1331 GenMulLong(opcode, rl_dest, rl_src1, rl_src2);
1336 GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true);
1341 GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false);
1346 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true);
1351 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true);
1356 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true);
1369 bool X86Mir2Lir::GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val) {
1384 StoreValueWide(rl_dest, rl_src1);
1387 GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1);
1391 if (!BadOverlap(rl_src1, rl_dest)) {
1392 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
1393 RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, rl_src1,
1406 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg);
1407 bool src1_in_reg = rl_src1.location == kLocPhysReg;
1408 int displacement = SRegOffset(rl_src1.s_reg_low);
1413 GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo);
1414 GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi);
1416 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo);
1417 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi);
1428 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg());
1447 void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
1449 if (rl_src1.is_const) {
1450 std::swap(rl_src1, rl_src2);
1454 if (GenMulLongConst(rl_dest, rl_src1, mir_graph_->ConstantValueWide(rl_src2))) {
1463 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
1466 if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() &&
1469 } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() &&
1471 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg());
1472 } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() &&
1476 OpRegCopy(rl_result.reg, rl_src1.reg);
1485 bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) ==
1490 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg);
1494 bool src1_in_reg = rl_src1.location == kLocPhysReg;
1499 NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg());
1501 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32,
1531 NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg());
1533 int displacement = SRegOffset(rl_src1.s_reg_low);
1565 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg());
1567 int displacement = SRegOffset(rl_src1.s_reg_low);
1667 void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1,
1688 RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg);
1705 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg);
1709 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
1711 if (IsTemp(rl_src1.reg)) {
1712 GenLongRegOrMemOp(rl_src1, rl_src2, op);
1717 rl_src1 = ForceTempWide(rl_src1);
1718 GenLongRegOrMemOp(rl_src1, rl_src2, op);
1720 GenLongRegOrMemOp(rl_src2, rl_src1, op);
1726 rl_src1 = ForceTempWide(rl_src1);
1727 GenLongRegOrMemOp(rl_src1, rl_src2, op);
1730 if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) {
1731 GenLongRegOrMemOp(rl_src1, rl_src2, op);
1736 rl_src1 = ForceTempWide(rl_src1);
1737 GenLongRegOrMemOp(rl_src1, rl_src2, op);
1739 GenLongRegOrMemOp(rl_src2, rl_src1, op);
1745 rl_src1 = ForceTempWide(rl_src1);
1746 GenLongRegOrMemOp(rl_src1, rl_src2, op);
1750 StoreFinalValueWide(rl_dest, rl_src1);
1937 void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
1947 GenDivRemLongLit(rl_dest, rl_src1, imm, is_div);
1956 LoadValueDirectWideFixed(rl_src1, rs_r0q);
2274 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
2282 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode);
2284 DCHECK(rl_src1.is_const);
2285 isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode);
2291 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode);
2293 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
2305 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode);
2308 DCHECK(rl_src1.is_const);
2309 isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode);
2319 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
2551 bool X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1,
2562 rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) {
2564 OpRegCopy(rl_dest.reg, rl_src1.reg);
2570 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
2572 RegLocation rl_result = ForceTempWide(rl_src1);
2584 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg);
2587 if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg &&
2588 rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() &&
2589 rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) {
2603 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
2604 DCHECK_EQ(rl_src1.location, kLocPhysReg);
2607 RegLocation rl_result = ForceTempWide(rl_src1);
2966 RegLocation rl_src1, RegLocation rl_shift) {
2968 Mir2Lir::GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
3016 rl_src1 = LoadValueWide(rl_src1, kCoreReg);
3018 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg);
