Lines Matching refs:instructions
50 // can be defined to enable ARMv7 and VFPv3 instructions when building the
243 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
244 // Patch the code at the current address with the supplied instructions.
246 Instr* instr = reinterpret_cast<Instr*>(instructions);
257 // Additional guard instructions can be added if required.
404 // Specific instructions, constants, and masks.
452 // A mask for the Rd register for push, pop, ldr, str instructions.
774 // Here are the instructions we need to emit:
814 // Patch with a sequence of mov/orr/orr instructions.
919 // Keep track of the last bound label so we don't eliminate any instructions
1055 // instructions - either mov or ldr. The mov might actually be two
1056 // instructions mov or movw followed by movt so including the actual
1057 // instruction two or three instructions will be generated.
1268 // Branch instructions.
1315 // Data-processing instructions.
1402 // Don't allow nop instructions in the form mov rn, rn to be generated using
1404 // or MarkCode(int/NopMarkerTypes) pseudo instructions.
1415 // instructions.
1421 // When the label is bound, these instructions will be patched with a
1422 // sequence of movw/movt or mov/orr/orr instructions. They will load the
1437 // patches the instructions.
1474 // Multiply instructions.
1561 // Miscellaneous arithmetic instructions.
1570 // Saturating instructions.
1594 // Bitfield manipulation instructions.
1777 // Status register access instructions.
1808 // Load/Store instructions.
1874 // Preload instructions.
1893 // Load/Store multiple instructions.
1923 // Exception-generating instructions and debugging support.
1965 // Coprocessor instructions.
3019 // Pseudo instructions.
3237 void Assembler::BlockConstPoolFor(int instructions) {
3245 int pc_limit = pc_offset() + instructions * kInstrSize;
