Lines Matching refs:reg
17 #define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) __##reg
19 #define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) reg
421 DNBArchMachPPC::GetRegisterValue(int set, int reg, DNBRegisterValue *value) const
425 switch (reg)
429 reg = e_regNumGPR_srr0;
434 reg = e_regNumGPR_r1;
446 reg = e_regNumGPR_lr;
451 reg = e_regNumGPR_srr1;
462 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
469 if (reg < k_num_gpr_registers)
471 value->value.uint32 = (&m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0))[reg];
477 if (reg < 32)
479 value->value.float64 = m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpregs)[reg];
482 else if (reg == 32)
490 if (reg < k_num_exc_registers)
492 value->value.uint32 = (&m_state.exc.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(dar))[reg];
498 if (reg < k_num_vec_registers)
500 if (reg < 33) // FP0 - FP31 and VSCR
503 value->value.v_uint32[0] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][0];
504 value->value.v_uint32[1] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][1];
505 value->value.v_uint32[2] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][2];
506 value->value.v_uint32[3] = m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg][3];
509 else if (reg == 34) // VRVALID
