Lines Matching refs:Reg
61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
98 // Create a new GroupNode for Reg. Reg's existing GroupNode must
103 GroupNodeIndices[Reg] = idx;
107 bool AggressiveAntiDepState::IsLive(unsigned Reg)
111 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
161 unsigned Reg = *AI;
162 State->UnionGroups(Reg, 0);
163 KillIndices[Reg] = BB->size();
164 DefIndices[Reg] = ~0u;
174 unsigned Reg = *I;
175 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
176 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
205 // If Reg is current live, then mark that it can't be renamed as
211 if (State->IsLive(Reg)) {
212 DEBUG(if (State->GetGroup(Reg) != 0)
213 dbgs() << " " << TRI->getName(Reg) << "=g" <<
214 State->GetGroup(Reg) << "->g0(region live-out)");
215 State->UnionGroups(Reg, 0);
216 } else if ((DefIndices[Reg] < InsertPosIndex)
217 && (DefIndices[Reg] >= Count)) {
218 DefIndices[Reg] = Count;
230 unsigned Reg = MO.getReg();
231 if (Reg == 0)
236 Op = MI->findRegisterUseOperand(Reg, true);
238 Op = MI->findRegisterDefOperand(Reg);
250 const unsigned Reg = MO.getReg();
251 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
265 unsigned Reg = P->getReg();
266 if (RegSet.count(Reg) == 0) {
268 RegSet.insert(Reg);
299 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
308 if (!State->IsLive(Reg)) {
309 KillIndices[Reg] = KillIdx;
310 DefIndices[Reg] = ~0u;
311 RegRefs.erase(Reg);
312 State->LeaveGroup(Reg);
314 dbgs() << header << TRI->getName(Reg); header = nullptr; });
315 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
318 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
326 dbgs() << header << TRI->getName(Reg); header = nullptr; });
350 unsigned Reg = MO.getReg();
351 if (Reg == 0) continue;
353 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
360 unsigned Reg = MO.getReg();
361 if (Reg == 0) continue;
363 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
370 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
371 State->UnionGroups(Reg, 0);
375 // partially defined here, so group those aliases with Reg.
376 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
379 State->UnionGroups(Reg, AliasReg);
380 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
390 RegRefs.insert(std::make_pair(Reg, RR));
400 unsigned Reg = MO.getReg();
401 if (Reg == 0) continue;
403 if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
406 // Update def for Reg and aliases.
407 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
414 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
453 unsigned Reg = MO.getReg();
454 if (Reg == 0) continue;
456 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
457 State->GetGroup(Reg));
462 HandleLastUse(Reg, Count, "(last-use)");
465 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
466 State->UnionGroups(Reg, 0);
474 RegRefs.insert(std::make_pair(Reg, RR));
488 unsigned Reg = MO.getReg();
489 if (Reg == 0) continue;
492 DEBUG(dbgs() << "=" << TRI->getName(Reg));
493 State->UnionGroups(FirstReg, Reg);
495 DEBUG(dbgs() << " " << TRI->getName(Reg));
496 FirstReg = Reg;
504 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
508 // Check all references that need rewriting for Reg. For each, use
515 Range = State->GetRegRefs().equal_range(Reg);
562 unsigned Reg = Regs[i];
563 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
564 SuperReg = Reg;
566 // If Reg has any references, then collect possible rename regs
567 if (RegRefs.count(Reg) > 0) {
568 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
570 BitVector BV = GetRenameRegisters(Reg);
571 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
582 unsigned Reg = Regs[i];
583 if (Reg == SuperReg) continue;
584 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
643 unsigned Reg = Regs[i];
645 if (Reg == SuperReg) {
648 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
655 // Check if Reg can be renamed to NewReg.
656 BitVector BV = RenameRegisterMap[Reg];
663 // Regs's kill, it's safe to replace Reg with NewReg. We
666 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
674 (KillIndices[Reg] > DefIndices[AliasReg])) {
684 // Record that 'Reg' can be renamed to 'NewReg'.
685 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
756 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
757 if (!State->IsLive(Reg))
758 DEBUG(dbgs() << " " << TRI->getName(Reg));
812 DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
