Lines Matching defs:NewReg
343 // be replaced by NewReg. Return true if any of their parent instructions may
348 // the two-address instruction also defines NewReg, as may happen with
352 // both NewReg and AntiDepReg covers it.
356 unsigned NewReg)
362 // operands, in case they may be assigned to NewReg. In this case antidep
367 // Handle cases in which this instruction defines NewReg.
372 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
376 CheckOper.getReg() != NewReg)
379 // Don't allow the instruction to define NewReg and AntiDepReg.
385 // NewReg.
389 // Don't allow inline asm to define NewReg at all. Who knows what it's
408 unsigned NewReg = Order[i];
410 if (NewReg == AntiDepReg) continue;
414 if (NewReg == LastNewReg) continue;
415 // If any instructions that define AntiDepReg also define the NewReg
418 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
419 // If NewReg is dead and NewReg's most recent def is not before
420 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
423 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
424 && "Kill and Def maps aren't consistent for NewReg!");
425 if (KillIndices[NewReg] != ~0u ||
426 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
427 KillIndices[AntiDepReg] > DefIndices[NewReg])
429 // If NewReg overlaps any of the forbidden registers, we can't use it.
433 if (TRI->regsOverlap(NewReg, *it)) {
438 return NewReg;
652 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
659 << " using " << TRI->getName(NewReg) << "!\n");
665 Q->second->setReg(NewReg);
674 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
680 Classes[NewReg] = Classes[AntiDepReg];
681 DefIndices[NewReg] = DefIndices[AntiDepReg];
682 KillIndices[NewReg] = KillIndices[AntiDepReg];
683 assert(((KillIndices[NewReg] == ~0u) !=
684 (DefIndices[NewReg] == ~0u)) &&
685 "Kill and Def maps aren't consistent for NewReg!");
695 LastNewReg[AntiDepReg] = NewReg;
