Lines Matching full:live
17 // Register live intervals: Registers must be defined only once, and must be
103 // Vregs that must be live in because they are used without being
111 // Regs defined in MBB and live out. Note that vregs passing through may
112 // be live out without being mentioned here.
175 // Live-out registers are either in regsLiveOut or vregsPassed.
506 // If this block has allocatable physical registers live-in, check that
514 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
680 report("MBB live-in list contains non-physical register", MBB);
972 *OS << "Live stack: " << LI << '\n';
976 *OS << "Live stack: " << LI << '\n';
1014 report("No live segment at use", MO, MONum);
1015 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1019 report("Live range continues after kill flag", MO, MONum);
1032 report("No live segment at use", MO, MONum);
1033 *OS << UseIdx << " is not live in " << LI << '\n';
1038 report("Live range continues after kill flag", MO, MONum);
1039 *OS << "Live range: " << LI << '\n';
1042 report("Virtual register has no live interval", MO, MONum);
1057 // We don't know which virtual registers are live in, so only complain
1059 // must be live in. PHI instructions are handled separately.
1081 // Check LiveInts for a live segment, but only for virtual registers.
1096 report("No live segment at def", MO, MONum);
1097 *OS << DefIdx << " is not live in " << LI << '\n';
1103 report("Live range continues after dead def flag", MO, MONum);
1104 *OS << "Live range: " << LI << '\n';
1108 report("Virtual register has no Live interval", MO, MONum);
1154 // can pass through an MBB live, but may not be live every time. It is assumed
1157 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1193 // First push live-in regs to predecessors' vregsRequired.
1239 report("PHI operand is not live-out from predecessor",
1271 // Check for killed virtual registers that should be live out.
1278 report("Virtual register killed in block, but needed live out.", &MBB);
1312 << " must be live through the block.\n";
1318 << " is not needed live through the block.\n";
1335 report("Missing live interval for virtual register", MF);
1360 report("Valno not live at def and not marked unused", MF, LR);
1366 report("Live segment at def has different valno", MF, LR);
1368 << " where valno #" << DefVNI->id << " is live\n";
1441 assert(VNI && "Live segment has no valno");
1444 report("Foreign valno in live segment", MF, LR);
1449 report("Live segment valno is marked unused", MF, LR);
1455 report("Bad start of live segment, no basic block", MF, LR);
1461 report("Live segment must begin at MBB entry or valno def", MBB, LR);
1468 report("Bad end of live segment, no basic block", MF, LR);
1473 // No more checks for live-out segments.
1482 // The live segment is ending inside EndMBB
1486 report("Live segment doesn't end at a valid instruction", EndMBB, LR);
1493 report("Live segment ends at B slot of an instruction", EndMBB, LR);
1501 report("Live segment ending at dead slot spans instructions", EndMBB, LR);
1506 // A live segment can only end at an early-clobber slot if it is being
1510 report("Live segment ending at early clobber slot must be "
1519 // A live segment can end with either a redefinition, a kill flag on a
1530 report("Instruction ending live segment doesn't read the register", MI);
1536 // Now check all the basic blocks in this live segment.
1538 // Is this live segment the beginning of a non-PHIDef VN?
1540 // Not live-in to any blocks.
1561 // Check that VNI is live-out of all predecessors.
1567 // All predecessors must have a live-out value.
1569 report("Register not marked live out of predecessor", *PI, LR);
1570 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1571 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1578 report("Different value live out of predecessor", *PI, LR);
1579 *OS << "Valno #" << PVNI->id << " live out of BB#"
1581 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1608 report("Multiple connected components in live interval", MF, LI);
