Lines Matching defs:PhysReg
248 unsigned PhysReg;
253 // Interference for PhysReg.
261 PhysReg = Reg;
281 /// Candidate info for each PhysReg in AllocationOrder.
338 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
343 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
365 unsigned PhysReg, unsigned &CostPerUseLimit,
572 unsigned PhysReg;
573 while ((PhysReg = Order.next()))
574 if (!Matrix->checkInterference(VirtReg, PhysReg))
576 if (!PhysReg || Order.isHint())
577 return PhysReg;
579 // PhysReg is available, but there may be a better choice.
595 unsigned Cost = TRI->getCostPerUse(PhysReg);
599 return PhysReg;
601 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
604 return CheapReg ? CheapReg : PhysReg;
614 unsigned PhysReg;
615 while ((PhysReg = Order.next())) {
616 if (PhysReg == PrevReg)
619 MCRegUnitIterator Units(PhysReg, TRI);
626 // If no units have interference, break out with the current PhysReg.
630 if (PhysReg)
632 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
634 return PhysReg;
667 /// PhysReg can be evicted.
670 /// @param PhysReg Desired register for assignment.
671 /// @param IsHint True when PhysReg is VirtReg's preferred register.
675 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
678 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
695 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
745 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
755 /// from being assigned to Physreg. This assumes that canEvictInterference
757 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
766 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
771 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
794 /// tryEvict - Try to evict all interferences for a physreg.
797 /// @return Physreg to assign VirtReg, or 0.
834 while (unsigned PhysReg = Order.next(OrderLimit)) {
835 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
840 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
842 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
847 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
851 BestPhys = PhysReg;
871 /// interference pattern in Physreg and its aliases. Add the constraints to
1017 if (Cand.PhysReg)
1043 // Compact regions don't correspond to any physreg.
1049 // that all the through blocks have interference when PhysReg is unset.
1253 // - Candidate intervals can be assigned to Cand.PhysReg.
1327 while (unsigned PhysReg = Order.next()) {
1328 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
1338 if (i == BestCand || !GlobalCand[i].PhysReg)
1353 Cand.reset(IntfCache, PhysReg);
1358 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1361 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
1369 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1418 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1427 assert(!Cand.PhysReg && "Compact region has no physreg");
1578 /// in order to use PhysReg between two entries in SA->UseSlots.
1582 void RAGreedy::calcGapWeights(unsigned PhysReg,
1598 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1633 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1745 while (unsigned PhysReg = Order.next()) {
1747 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1748 calcGapWeights(PhysReg, GapWeight);
1751 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1770 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1884 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1895 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1896 if (PhysReg || !NewVRegs.empty())
1897 return PhysReg;
1912 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1913 return PhysReg;
1920 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1921 if (PhysReg || !NewVRegs.empty())
1922 return PhysReg;
1934 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1935 /// recolored to free \p PhysReg.
1937 /// the live intervals that need to be recolored in order to free \p PhysReg
1942 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
1947 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2041 while (unsigned PhysReg = Order.next()) {
2043 << PrintReg(PhysReg, TRI) << '\n');
2048 if (Matrix->checkInterference(VirtReg, PhysReg) >
2055 // Early give up on this PhysReg if it is obvious we cannot recolor all
2057 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2064 // with VirtReg on PhysReg (or one of its aliases).
2081 // Do as if VirtReg was assigned to PhysReg so that the underlying
2084 Matrix->assign(VirtReg, PhysReg);
2095 return PhysReg;
2099 << PrintReg(PhysReg, TRI) << '\n');
2134 unsigned PhysReg;
2135 PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1);
2136 if (PhysReg == ~0u || !PhysReg)
2139 << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n');
2140 Matrix->assign(*LI, PhysReg);
2182 unsigned PhysReg,
2190 return PhysReg;
2207 return PhysReg;
2213 return PhysReg;
2248 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) {
2251 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
2259 unsigned CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2266 return PhysReg;
2277 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit))
2278 return PhysReg;
2299 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
2300 if (PhysReg || !NewVRegs.empty())
2301 return PhysReg;
