Lines Matching full:intf
254 InterferenceCache::Cursor Intf;
263 Intf.setPhysReg(Cache, Reg);
703 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
704 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
707 if (getStage(*Intf) == RS_Done)
716 (Intf->isSpillable() ||
718 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
720 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
729 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
732 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
739 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
744 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
745 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
780 LiveInterval *Intf = Intfs[i];
782 if (!VRM->hasPhys(Intf->reg))
784 Matrix->unassign(*Intf);
785 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
786 VirtReg.isSpillable() < Intf->isSpillable()) &&
788 ExtraRegInfo[Intf->reg].Cascade = Cascade;
790 NewVRegs.push_back(Intf->reg);
875 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
887 Intf.moveToBlock(BC.Number);
892 if (!Intf.hasInterference())
900 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
902 else if (Intf.first() < BI.FirstInstr)
904 else if (Intf.first() < BI.LastInstr)
910 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
912 else if (Intf.last() > BI.LastInstr)
914 else if (Intf.last() > BI.FirstInstr)
933 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
942 Intf.moveToBlock(Number);
944 if (!Intf.hasInterference()) {
958 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
964 if (Intf.last() >= SA->getLastSplitPoint(Number))
1018 addThroughConstraints(Cand.Intf, NewBlocks);
1052 // The static split cost will be zero since Cand.Intf reports no interference.
1054 if (!addSplitConstraints(Cand.Intf, Cost)) {
1125 Cand.Intf.moveToBlock(Number);
1126 if (Cand.Intf.hasInterference()) {
1176 Cand.Intf.moveToBlock(Number);
1177 IntfIn = Cand.Intf.first();
1185 Cand.Intf.moveToBlock(Number);
1186 IntfOut = Cand.Intf.last();
1225 Cand.Intf.moveToBlock(Number);
1226 IntfIn = Cand.Intf.first();
1233 Cand.Intf.moveToBlock(Number);
1234 IntfOut = Cand.Intf.last();
1357 if (!addSplitConstraints(Cand.Intf, Cost)) {
1958 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
1959 // If Intf is done and sit on the same register class as VirtReg,
1961 if ((getStage(*Intf) == RS_Done &&
1962 MRI->getRegClass(Intf->reg) == CurRC) ||
1963 FixedRegisters.count(Intf->reg)) {
1967 RecoloringCandidates.insert(Intf);
