Lines Matching refs:SUnit
125 std::vector<SUnit*> PendingQueue;
144 std::vector<SUnit*> LiveRegDefs;
145 std::vector<SUnit*> LiveRegGens;
148 // Each interference is an SUnit and set of physical registers.
149 SmallVector<SUnit*, 4> Interferences;
150 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
159 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
187 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
193 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
197 /// AddPred - adds a predecessor edge to SUnit SU.
200 void AddPred(SUnit *SU, const SDep &D) {
205 /// RemovePred - removes a predecessor edge from SUnit SU.
208 void RemovePred(SUnit *SU, const SDep &D) {
214 bool isReady(SUnit *SU) {
219 void ReleasePred(SUnit *SU, const SDep *PredEdge);
220 void ReleasePredecessors(SUnit *SU);
223 void AdvancePastStalls(SUnit *SU);
224 void EmitNode(SUnit *SU);
225 void ScheduleNodeBottomUp(SUnit*);
227 void UnscheduleNodeBottomUp(SUnit*);
229 void BacktrackBottomUp(SUnit*, SUnit*);
230 SUnit *CopyAndMoveSuccessors(SUnit*);
231 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
234 SmallVectorImpl<SUnit*>&);
235 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
239 SUnit *PickNodeToScheduleBottomUp();
242 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
244 SUnit *CreateNewSUnit(SDNode *N) {
246 SUnit *NewNode = newSUnit(N);
253 /// CreateClone - Creates a new SUnit from an existing one.
255 SUnit *CreateClone(SUnit *N) {
257 SUnit *NewNode = Clone(N);
366 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
367 SUnit *PredSU = PredEdge->getSUnit();
526 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
528 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
536 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
559 SUnit *Def = &SUnits[N->getNodeId()];
623 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
663 /// Record this SUnit in the HazardRecognizer.
665 void ScheduleDAGRRList::EmitNode(SUnit *SU) {
702 static void resetVRegCycle(SUnit *SU);
707 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
718 // backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the
741 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
793 SUnit *PredSU = PredEdge->getSUnit();
806 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
810 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
852 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
892 std::vector<SUnit*>::const_iterator I = (Sequence.end() - LookAhead);
894 for (std::vector<SUnit*>::const_iterator E = Sequence.end(); I != E; ++I) {
895 SUnit *SU = *I;
905 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
906 SUnit *OldSU = Sequence.back();
927 static bool isOperandOf(const SUnit *SU, SDNode *N) {
938 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
946 SUnit *NewSU;
988 SUnit *LoadSU;
1000 SUnit *NewSU = CreateNewSUnit(N);
1023 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1032 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1060 SUnit *SuccDep = D.getSUnit();
1072 SUnit *SuccDep = D.getSUnit();
1103 // New SUnit has the exact same predecessors.
1104 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1111 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1112 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1116 SUnit *SuccSU = I->getSUnit();
1136 /// scheduled successors of the given SUnit to the last copy.
1137 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
1140 SmallVectorImpl<SUnit*> &Copies) {
1141 SUnit *CopyFromSU = CreateNewSUnit(nullptr);
1145 SUnit *CopyToSU = CreateNewSUnit(nullptr);
1151 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1152 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1156 SUnit *SuccSU = I->getSUnit();
1206 /// specified register def of the specified SUnit clobbers any "live" registers.
1207 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1208 std::vector<SUnit*> &LiveRegDefs,
1229 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask,
1230 std::vector<SUnit*> &LiveRegDefs,
1257 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
1266 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1333 SUnit *SU = Interferences[i-1];
1359 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
1360 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop();
1389 SUnit *TrySU = Interferences[i];
1394 SUnit *BtSU = nullptr;
1437 SUnit *TrySU = Interferences[0];
1441 SUnit *LRDef = LiveRegDefs[Reg];
1454 SUnit *NewDef = nullptr;
1462 SmallVector<SUnit*, 2> Copies;
1489 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
1504 SUnit *SU = PickNodeToScheduleBottomUp();
1535 struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1536 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
1545 bool operator()(SUnit* left, SUnit* right) const {
1564 bool operator()(SUnit* left, SUnit* right) const;
1578 bool operator()(SUnit* left, SUnit* right) const;
1592 bool isReady(SUnit *SU, unsigned CurCycle) const;
1594 bool operator()(SUnit* left, SUnit* right) const;
1609 bool isReady(SUnit *SU, unsigned CurCycle) const;
1611 bool operator()(SUnit* left, SUnit* right) const;
1616 std::vector<SUnit*> Queue;
1622 std::vector<SUnit> *SUnits;
1672 void initNodes(std::vector<SUnit> &sunits) override;
1674 void addNode(const SUnit *SU) override;
1676 void updateNode(const SUnit *SU) override;
1684 unsigned getNodePriority(const SUnit *SU) const;
1686 unsigned getNodeOrdering(const SUnit *SU) const {
1694 void push(SUnit *U) override {
1700 void remove(SUnit *SU) override {
1703 std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(),
1715 bool HighRegPressure(const SUnit *SU) const;
1717 bool MayReduceRegPressure(SUnit *SU) const;
1719 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1721 void scheduledNode(SUnit *SU) override;
1723 void unscheduledNode(SUnit *SU) override;
1726 bool canClobber(const SUnit *SU, const SUnit *Op);
1733 static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) {
1734 std::vector<SUnit *>::iterator Best = Q.begin();
1735 for (std::vector<SUnit *>::iterator I = std::next(Q.begin()),
1739 SUnit *V = *Best;
1747 SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) {
1775 bool isReady(SUnit *U) const override {
1779 SUnit *pop() override {
1782 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG);
1790 std::vector<SUnit*> DumpQueue = Queue;
1793 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
1824 static int checkSpecialNodes(const SUnit *left, const SUnit *right) {
1835 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
1841 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1844 SUnit *PredSU = I->getSUnit();
1870 void RegReductionPQBase::addNode(const SUnit *SU) {
1877 void RegReductionPQBase::updateNode(const SUnit *SU) {
1884 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
1939 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1943 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1947 SUnit *PredSU = I->getSUnit();
1965 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
1990 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
1993 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1997 SUnit *PredSU = I->getSUnit();
2030 void RegReductionPQBase::scheduledNode(SUnit *SU) {
2037 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2041 SUnit *PredSU = I->getSUnit();
2099 void RegReductionPQBase::unscheduledNode(SUnit *SU) {
2119 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2123 SUnit *PredSU = I->getSUnit();
2186 static unsigned closestSucc(const SUnit *SU) {
2188 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2205 static unsigned calcMaxScratches(const SUnit *SU) {
2207 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2217 static bool hasOnlyLiveInOpers(const SUnit *SU) {
2219 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2222 const SUnit *PredSU = I->getSUnit();
2240 static bool hasOnlyLiveOutUses(const SUnit *SU) {
2242 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2245 const SUnit *SuccSU = I->getSUnit();
2269 static void initVRegCycle(SUnit *SU) {
2280 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2289 static void resetVRegCycle(SUnit *SU) {
2293 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2296 SUnit *PredSU = I->getSUnit();
2305 // Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This
2307 static bool hasVRegCycleUse(const SUnit *SU) {
2312 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2327 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
2337 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
2388 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
2492 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2500 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2519 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2534 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2566 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2576 static bool canEnableCoalescing(SUnit *SU) {
2600 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2659 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
2682 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2703 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU,
2713 for (SUnit::const_succ_iterator SI = SU->Succs.begin(), SE = SU->Succs.end();
2715 SUnit *SuccSU = SI->getSUnit();
2716 for (SUnit::const_pred_iterator PI = SuccSU->Preds.begin(),
2740 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
2811 SUnit *SU = &(*SUnits)[i];
2829 SUnit *PredSU = nullptr;
2830 for (SUnit::const_pred_iterator II = SU->Preds.begin(),
2854 for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),
2856 SUnit *PredSuccSU = II->getSUnit();
2879 SUnit *SuccSU = Edge.getSUnit();
2902 SUnit *SU = &(*SUnits)[i];
2921 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
2923 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
2926 SUnit *SuccSU = I->getSUnit();
