Lines Matching refs:N0
1206 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1219 getBooleanContents(N0->getValueType(0));
1228 if (isa<ConstantSDNode>(N0.getNode()) &&
1230 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1231 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1239 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1240 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1241 N0.getOperand(1).getOpcode() == ISD::Constant) {
1243 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1245 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1255 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1256 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1261 SDValue CTPOP = N0;
1263 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1264 CTPOP = N0.getOperand(0);
1267 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1286 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1288 unsigned MinBits = N0.getValueSizeInBits();
1290 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1292 MinBits = N0->getOperand(0).getValueSizeInBits();
1293 PreZExt = N0->getOperand(0);
1294 } else if (N0->getOpcode() == ISD::AND) {
1296 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1299 PreZExt = N0->getOperand(0);
1301 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1305 PreZExt = N0;
1327 N0.getOpcode() == ISD::AND && C1 == 0 &&
1328 N0.getNode()->hasOneUse() &&
1329 isa<LoadSDNode>(N0.getOperand(0)) &&
1330 N0.getOperand(0).getNode()->hasOneUse() &&
1331 isa<ConstantSDNode>(N0.getOperand(1))) {
1332 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1336 unsigned origWidth = N0.getValueType().getSizeInBits();
1343 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1382 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1383 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1417 EVT newVT = N0.getOperand(0).getValueType();
1424 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1426 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1433 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1435 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1437 EVT ExtDstTy = N0.getValueType();
1446 EVT Op0Ty = N0.getOperand(0).getValueType();
1448 ZextOp = N0.getOperand(0);
1451 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1466 if (N0.getOpcode() == ISD::SETCC &&
1467 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1470 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1472 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1474 N0.getOperand(0).getValueType().isInteger());
1476 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1477 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1480 if ((N0.getOpcode() == ISD::XOR ||
1481 (N0.getOpcode() == ISD::AND &&
1482 N0.getOperand(0).getOpcode() == ISD::XOR &&
1483 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1484 isa<ConstantSDNode>(N0.getOperand(1)) &&
1485 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1488 unsigned BitWidth = N0.getValueSizeInBits();
1489 if (DAG.MaskedValueIsZero(N0,
1494 if (N0.getOpcode() == ISD::XOR)
1495 Val = N0.getOperand(0);
1497 assert(N0.getOpcode() == ISD::AND &&
1498 N0.getOperand(0).getOpcode() == ISD::XOR);
1500 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1501 N0.getOperand(0).getOperand(0),
1502 N0.getOperand(1));
1510 getBooleanContents(N0->getValueType(0)) ==
1512 SDValue Op0 = N0;
1569 return DAG.getSetCC(dl, VT, N0,
1584 return DAG.getSetCC(dl, VT, N0,
1601 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1604 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1608 return DAG.getSetCC(dl, VT, N0,
1609 DAG.getConstant(MinVal, N0.getValueType()),
1613 return DAG.getSetCC(dl, VT, N0,
1614 DAG.getConstant(MaxVal, N0.getValueType()),
1623 return DAG.getSetCC(dl, VT, N0,
1633 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1638 (VT == N0.getValueType() ||
1639 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1640 N0.getOpcode() == ISD::AND)
1642 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1644 getPointerTy() : getShiftAmountTy(N0.getValueType());
1649 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1657 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1667 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1669 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1674 getPointerTy() : getShiftAmountTy(N0.getValueType());
1675 EVT CmpTy = N0.getValueType();
1676 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1702 getPointerTy() : getShiftAmountTy(N0.getValueType());
1703 EVT CmpTy = N0.getValueType();
1704 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1713 if (isa<ConstantFPSDNode>(N0.getNode())) {
1715 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1738 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1742 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1749 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1750 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1752 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1753 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1755 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1756 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1758 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1759 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1762 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1763 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1765 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1766 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1768 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1769 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1771 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1772 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1778 if (N0 == N1) {
1782 switch (getBooleanContents(N0.getValueType())) {
1793 if (N0.getValueType().isInteger()) {
1805 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1806 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1810 N0.getValueType().isInteger()) {
1811 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1812 N0.getOpcode() == ISD::XOR) {
1814 if (N0.getOpcode() == N1.getOpcode()) {
1815 if (N0.getOperand(0) == N1.getOperand(0))
1816 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1817 if (N0.getOperand(1) == N1.getOperand(1))
1818 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1819 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1821 if (N0.getOperand(0) == N1.getOperand(1))
1822 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1824 if (N0.getOperand(1) == N1.getOperand(0))
1825 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1835 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1837 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1838 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1841 N0.getValueType()), Cond);
1845 if (N0.getOpcode() == ISD::XOR)
1848 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1850 DAG.getSetCC(dl, VT, N0.getOperand(0),
1853 N0.getValueType()),
1858 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1859 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1861 DAG.getSetCC(dl, VT, N0.getOperand(1),
1864 N0.getValueType()),
1878 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1879 if (N0.getOperand(0) == N1)
1880 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1881 DAG.getConstant(0, N0.getValueType()), Cond);
1882 if (N0.getOperand(1) == N1) {
1883 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1884 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1885 DAG.getConstant(0, N0.getValueType()), Cond);
1886 if (N0.getNode()->hasOneUse()) {
1887 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1893 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1902 if (N1.getOperand(0) == N0)
1905 if (N1.getOperand(1) == N0) {
1912 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1913 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1925 if (N0.getOpcode() == ISD::AND)
1926 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1930 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1932 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1937 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1938 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1942 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1951 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1955 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1956 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1961 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1965 Temp = DAG.getNOT(dl, N0, MVT::i1);
1966 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1973 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1979 Temp = DAG.getNOT(dl, N0, MVT::i1);
1980 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1987 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1992 DCI.AddToWorklist(N0.getNode());
1994 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1996 return N0;
