Lines Matching defs:regA
106 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
112 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
116 unsigned RegA, unsigned RegB, unsigned Dist);
494 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
495 if (RegA == RegB)
497 if (!RegA || !RegB)
499 return TRI->regsOverlap(RegA, RegB);
507 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
543 unsigned ToRegA = getMappedReg(regA, DstRegMap);
593 unsigned RegA = MI->getOperand(0).getReg();
594 SrcRegMap[RegA] = FromRegC;
603 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
613 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
622 unsigned RegA, unsigned RegB,
653 SrcRegMap.erase(RegA);
1099 unsigned regA = MI.getOperand(DstIdx).getReg();
1106 if (TargetRegisterInfo::isVirtualRegister(regA))
1107 scanUses(regA);
1128 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1156 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1158 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1218 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1356 unsigned RegA = DstMO.getReg();
1363 if (RegA == RegB) {
1370 LastCopiedReg = RegA;
1382 MI->getOperand(i).getReg() != RegA);
1387 TII->get(TargetOpcode::COPY), RegA);
1393 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1394 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1401 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1415 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1416 LiveInterval &LI = LIS->getInterval(RegA);
1434 // Make sure regA is a legal regclass for the SrcIdx operand.
1435 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1437 MRI->constrainRegClass(RegA, RC);
1438 MO.setReg(RegA);
1440 // by SubRegB is compatible with RegA with no subregister. So regardless of
1445 SrcRegMap[RegA] = RegB;
