Lines Matching full:hsub
1163 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1164 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1316 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1320 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
2239 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
3075 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3079 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3083 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3104 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3108 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3112 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3682 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3687 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3694 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3699 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3740 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3745 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3752 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3757 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3772 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3777 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3803 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3808 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4480 hsub),
4511 hsub),
