Lines Matching full:vreg
624 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
630 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
927 assert(Op.isReg() && "Non-register vreg operand!");
929 O << getRegisterName(Reg, AArch64::vreg);
1188 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
