Lines Matching defs:OpIdx
103 unsigned OpIdx);
154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
155 return getMachineOpValue(MI, MI.getOperand(OpIdx));
239 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
267 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
269 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
271 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
347 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
348 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
349 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
350 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
351 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
352 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
922 unsigned OpIdx) {
925 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
926 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
1015 unsigned OpIdx = 0;
1017 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1024 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1032 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1049 Binary |= getMachineOpValue(MI, OpIdx++);
1051 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1052 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1062 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1063 ++OpIdx;
1072 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1073 ++OpIdx;
1078 const MachineOperand &MO = MI.getOperand(OpIdx);
1081 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1117 unsigned OpIdx = 0;
1123 ++OpIdx;
1132 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1139 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1142 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1143 ++OpIdx;
1145 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1147 ? 0 : MI.getOperand(OpIdx+1).getImm();
1188 unsigned OpIdx = 0;
1194 ++OpIdx;
1199 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1203 ++OpIdx;
1210 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1213 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1214 ++OpIdx;
1216 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1218 ? 0 : MI.getOperand(OpIdx+1).getImm();
1273 unsigned OpIdx = 0;
1275 ++OpIdx;
1278 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1289 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1316 unsigned OpIdx = 0;
1318 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1321 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1324 Binary |= getMachineOpValue(MI, OpIdx++);
1327 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1331 if (MCID.getNumOperands() > OpIdx &&
1332 !MCID.OpInfo[OpIdx].isPredicate() &&
1333 !MCID.OpInfo[OpIdx].isOptionalDef())
1334 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1348 unsigned OpIdx = 0;
1351 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1353 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1354 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1362 ++OpIdx;
1368 if (MI.getOperand(OpIdx).isImm() &&
1369 !MCID.OpInfo[OpIdx].isPredicate() &&
1370 !MCID.OpInfo[OpIdx].isOptionalDef())
1371 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1391 unsigned OpIdx = 0;
1394 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1396 const MachineOperand &MO = MI.getOperand(OpIdx++);
1397 if (OpIdx == MCID.getNumOperands() ||
1398 MCID.OpInfo[OpIdx].isPredicate() ||
1399 MCID.OpInfo[OpIdx].isOptionalDef()) {
1410 Binary |= getMachineOpValue(MI, OpIdx++);
1413 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1545 unsigned OpIdx) const {
1546 unsigned RegD = MI.getOperand(OpIdx).getReg();
1560 unsigned OpIdx) const {
1561 unsigned RegN = MI.getOperand(OpIdx).getReg();
1575 unsigned OpIdx) const {
1576 unsigned RegM = MI.getOperand(OpIdx).getReg();
1598 unsigned OpIdx = 0;
1604 Binary |= encodeVFPRd(MI, OpIdx++);
1607 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1608 ++OpIdx;
1612 Binary |= encodeVFPRn(MI, OpIdx++);
1614 if (OpIdx == MCID.getNumOperands() ||
1615 MCID.OpInfo[OpIdx].isPredicate() ||
1616 MCID.OpInfo[OpIdx].isOptionalDef()) {
1623 Binary |= encodeVFPRm(MI, OpIdx);
1691 unsigned OpIdx = 0;
1694 Binary |= encodeVFPRd(MI, OpIdx++);
1697 const MachineOperand &Base = MI.getOperand(OpIdx++);
1702 const MachineOperand &Offset = MI.getOperand(OpIdx);
1730 unsigned OpIdx = 0;
1732 ++OpIdx;
1735 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1746 Binary |= encodeVFPRd(MI, OpIdx+2);
1750 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1767 unsigned OpIdx) const {
1768 unsigned RegD = MI.getOperand(OpIdx).getReg();
1777 unsigned OpIdx) const {
1778 unsigned RegN = MI.getOperand(OpIdx).getReg();
1787 unsigned OpIdx) const {
1788 unsigned RegM = MI.getOperand(OpIdx).getReg();
1880 unsigned OpIdx = 0;
1881 Binary |= encodeNEONRd(MI, OpIdx++);
1882 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1883 ++OpIdx;
1884 Binary |= encodeNEONRm(MI, OpIdx);
1895 unsigned OpIdx = 0;
1896 Binary |= encodeNEONRd(MI, OpIdx++);
1897 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1898 ++OpIdx;
1899 Binary |= encodeNEONRn(MI, OpIdx++);
1900 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1901 ++OpIdx;
1902 Binary |= encodeNEONRm(MI, OpIdx);
