Lines Matching refs:Reg
85 unsigned Reg;
92 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
435 // VLDM/VSTM do not support DB mode without also updating the base reg.
504 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
632 unsigned Reg = memOps[i].Reg;
633 KilledRegs.insert(Reg);
634 Killer[Reg] = i;
642 unsigned Reg = memOps[i].Reg;
645 bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
646 Regs.push_back(std::make_pair(Reg, isKill));
686 unsigned Reg = Regs[i-memOpsBegin].first;
687 if (KilledRegs.count(Reg)) {
688 unsigned j = Killer[Reg];
689 int Idx = memOps[j].MBBI->findRegisterUseOperandIdx(Reg, true);
746 unsigned Reg = MO.getReg();
747 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
751 if (Reg != ARM::SP &&
1240 // the vestigal zero-reg offset register. When that's fixed, this clause
1362 unsigned Reg, bool RegDeadKill, bool RegUndef,
1370 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1376 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1531 unsigned Reg = MO.getReg();
1557 if (TRI->regsOverlap(Reg, I->MBBI->getOperand(0).getReg())) {
1570 MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI));
1583 MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill,
1591 MemOps.insert(I, MemOpQueueEntry(Offset, Reg, isKill,
1842 unsigned Reg = MO.getReg();
1843 if (MO.isDef() && TRI->regsOverlap(Reg, Base))
1845 if (Reg != Base && !MemRegs.count(Reg))
1846 AddedRegPressure.insert(Reg);
2061 // uses addrmode2, so we need an explicit offset reg. It should
2075 // uses addrmode2, so we need an explicit offset reg. It should
