Lines Matching refs:Latch
193 /// The desired flow is: phi ---> bump -+-> comparison-in-latch.
202 /// +-> comparison-in-latch (against upper_bound-bump),
209 /// couldn't be identified, or if the value in the latch's comparison
326 MachineBasicBlock *Latch = L->getLoopLatch();
327 if (!Header || !Preheader || !Latch)
348 // latch block, and see if is a result of an addition of form "reg+imm",
351 if (Phi->getOperand(i+1).getMBB() != Latch)
374 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
455 MachineBasicBlock *Latch = L->getLoopLatch();
456 if (!Latch)
474 else if (MBB == Latch)
482 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
490 assert (TB && "Latch block without a branch?");
561 assert(EndValue->isImm() && "Unrecognized latch comparison");
1011 // Is the induction variable bump feeding the latch condition?
1063 // When the exit and latch are not the same, use the latch block as the
1066 // loop latch may contains instrs. that need to be executed after the
1069 // Make sure the latch is a successor of the exit, otherwise it won't work.
1247 MachineBasicBlock *Latch = L->getLoopLatch();
1249 if (!Header || !Preheader || !Latch)
1262 // vreg1 = PHI ..., [ latch, vreg2 ]
1271 if (Phi->getOperand(i+1).getMBB() != Latch)
1298 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
1302 // Check if the latch branch is unconditional.
1307 // The latch does not go back to the header. Not a latch we know and love.
1419 MachineBasicBlock *Latch = L->getLoopLatch();
1423 if (!Latch || Header->hasAddressTaken())
1435 if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false))
1440 if (PB != Latch) {
1452 // the loop latch. Any additional predecessors of the header should
1469 // Copy all non-latch operands of a header's PHI node to the newly
1474 if (PredB == Latch)
1485 if (PredB != Latch) {
1497 // The header has only two predecessors, but the non-latch predecessor
1507 if (MO.getMBB() != Latch)
1523 if (PB != Latch) {
1534 // It can happen that the latch block will fall through into the header.
1537 bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
1541 TII->InsertBranch(*Latch, Header, nullptr, EmptyCond, DL);
