Lines Matching defs:ResTy
1360 EVT ResTy = Op->getValueType(0);
1363 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1482 EVT ResTy = Op->getValueType(0);
1484 SDValue One = DAG.getConstant(1, ResTy);
1485 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1487 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1488 DAG.getNOT(DL, Bit, ResTy));
1493 EVT ResTy = Op->getValueType(0);
1494 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1496 SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1498 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1837 EVT ResTy = Op->getValueType(0);
1839 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1842 // If ResTy is v2i64 then the type legalizer will break this node down into
1844 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
1848 EVT ResTy = Op->getValueType(0);
1850 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1851 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1866 EVT ResTy = Op->getValueType(0);
1867 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1868 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1933 EVT ResTy = Op->getValueType(0);
1934 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1935 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1942 EVT ResTy = Op->getValueType(0);
1943 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1944 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2017 EVT ResTy = Op->getValueType(0);
2018 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2019 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2152 EVT ResTy = Op->getValueType(0);
2157 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2271 EVT ResTy = Op->getValueType(0);
2278 if (ResTy.isInteger()) {
2281 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2321 EVT ResTy = Op->getValueType(0);
2327 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
2342 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
2368 if (ViaVecTy != ResTy)
2369 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2378 EVT ResTy = Node->getValueType(0);
2380 assert(ResTy.isVector());
2382 unsigned NumElts = ResTy.getVectorNumElements();
2383 SDValue Vector = DAG.getUNDEF(ResTy);
2385 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2413 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2457 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2471 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2476 int WtIdx = ResTy.getVectorNumElements();
2487 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2501 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2506 int WtIdx = ResTy.getVectorNumElements() + 1;
2517 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2531 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2536 int WtIdx = ResTy.getVectorNumElements();
2547 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2561 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2565 unsigned NumElts = ResTy.getVectorNumElements();
2578 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2592 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2604 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2618 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2630 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2642 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2648 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2653 int ResTyNumElts = ResTy.getVectorNumElements();
2688 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2696 EVT ResTy = Op->getValueType(0);
2698 if (!ResTy.is128BitVector())
2701 int ResTyNumElts = ResTy.getVectorNumElements();
2707 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2710 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2713 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2716 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2719 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2722 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2725 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2728 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
