Lines Matching refs:VSELECT
82 setTargetDAGCombine(ISD::VSELECT);
100 setTargetDAGCombine(ISD::VSELECT);
272 setOperationAction(ISD::VSELECT, Ty, Legal);
317 setOperationAction(ISD::VSELECT, Ty, Legal);
657 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
773 // Transform the DAG into an equivalent VSELECT.
774 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
985 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
986 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
987 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
988 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
989 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
990 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
991 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
992 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
1087 case ISD::VSELECT:
1572 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1577 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1585 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1590 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1595 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1598 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1602 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1605 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1635 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1636 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1640 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1641 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
