Lines Matching full:regclass
1766 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1767 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1772 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1773 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1776 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
1778 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1779 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1783 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1784 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1785 regclass:$dst4),
1790 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1791 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a, i32imm:$b),
1796 class StoreParamV2Inst<NVPTXRegClass regclass, string opstr> :
1797 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2,
1803 class StoreParamV4Inst<NVPTXRegClass regclass, string opstr> :
1804 NVPTXInst<(outs), (ins regclass:$val, regclass:$val1, regclass:$val2,
1805 regclass:$val3, i32imm:$a, i32imm:$b),
1810 class StoreRetvalInst<NVPTXRegClass regclass, string opstr> :
1811 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a),
1816 class StoreRetvalV2Inst<NVPTXRegClass regclass, string opstr> :
1817 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2, i32imm:$a),
1822 class StoreRetvalV4Inst<NVPTXRegClass regclass, string opstr> :
1824 (ins regclass:$val, regclass:$val2, regclass:$val3,
1825 regclass:$val4, i32imm:$a),
1972 class CallArgInst<NVPTXRegClass regclass> :
1973 NVPTXInst<(outs), (ins regclass:$a), "$a, ",
1974 [(CallArg (i32 0), regclass:$a)]>;
1976 class LastCallArgInst<NVPTXRegClass regclass> :
1977 NVPTXInst<(outs), (ins regclass:$a), "$a",
1978 [(LastCallArg (i32 0), regclass:$a)]>;
2039 class MoveParamInst<NVPTXRegClass regclass, string asmstr> :
2040 NVPTXInst<(outs regclass:$dst), (ins regclass:$src),
2042 [(set regclass:$dst, (MoveParam regclass:$src))]>;
2052 class PseudoUseParamInst<NVPTXRegClass regclass> :
2053 NVPTXInst<(outs), (ins regclass:$src),
2055 [(PseudoUseParam regclass:$src)]>;
2067 multiclass LD<NVPTXRegClass regclass> {
2068 def _avar : NVPTXInst<(outs regclass:$dst),
2073 def _areg : NVPTXInst<(outs regclass:$dst),
2078 def _areg_64 : NVPTXInst<(outs regclass:$dst),
2083 def _ari : NVPTXInst<(outs regclass:$dst),
2088 def _ari_64 : NVPTXInst<(outs regclass:$dst),
2093 def _asi : NVPTXInst<(outs regclass:$dst),
2109 multiclass ST<NVPTXRegClass regclass> {
2111 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2116 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2121 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2126 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2131 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2136 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2155 multiclass LD_VEC<NVPTXRegClass regclass> {
2156 def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2161 def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2166 def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2171 def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2176 def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2181 def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2186 def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2187 regclass:$dst3, regclass:$dst4),
2192 def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2193 regclass:$dst4),
2198 def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2199 regclass:$dst3, regclass:$dst4),
2204 def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2205 regclass:$dst4),
2211 def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2212 regclass:$dst3, regclass:$dst4),
2218 def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2219 regclass:$dst4),
2235 multiclass ST_VEC<NVPTXRegClass regclass> {
2237 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2242 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2247 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2252 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2258 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2264 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2270 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2276 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2282 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2288 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2295 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2302 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
