Lines Matching full:regclass
833 multiclass F_ATOMIC_2_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
836 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
842 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
844 def imm : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, IMMType:$b),
850 [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
853 multiclass F_ATOMIC_2<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
855 defm p32 : F_ATOMIC_2_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
857 defm p64 : F_ATOMIC_2_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
862 multiclass F_ATOMIC_2_NEG_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
865 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
880 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
883 multiclass F_ATOMIC_2_NEG<NVPTXRegClass regclass, string SpaceStr,
886 defm p32: F_ATOMIC_2_NEG_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
888 defm p64: F_ATOMIC_2_NEG_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
893 multiclass F_ATOMIC_3_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
896 def reg : NVPTXInst<(outs regclass:$dst),
897 (ins ptrclass:$addr, regclass:$b, regclass:$c),
903 [(set regclass:$dst,
904 (IntOp ptrclass:$addr, regclass:$b, regclass:$c))]>,
906 def imm1 : NVPTXInst<(outs regclass:$dst),
907 (ins ptrclass:$addr, IMMType:$b, regclass:$c),
913 [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, regclass:$c))]>,
915 def imm2 : NVPTXInst<(outs regclass:$dst),
916 (ins ptrclass:$addr, regclass:$b, IMMType:$c),
922 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b, imm:$c))]>,
924 def imm3 : NVPTXInst<(outs regclass:$dst),
931 [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, imm:$c))]>,
934 multiclass F_ATOMIC_3<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
936 defm p32 : F_ATOMIC_3_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
938 defm p64 : F_ATOMIC_3_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
1378 multiclass LDU_G<string TyStr, NVPTXRegClass regclass> {
1379 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1382 def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1385 def avar: NVPTXInst<(outs regclass:$result), (ins imemAny:$src),
1388 def ari : NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1391 def ari64 : NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1408 multiclass VLDU_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1409 def _areg32: NVPTXInst<(outs regclassregclass:$dst2),
1412 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1415 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1418 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1421 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1426 multiclass VLDU_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1427 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1428 regclass:$dst4), (ins Int32Regs:$src),
1430 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1431 regclass:$dst4), (ins Int64Regs:$src),
1433 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1434 regclass:$dst4), (ins MEMri:$src),
1436 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1437 regclass:$dst4), (ins MEMri64:$src),
1439 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1440 regclass:$dst4), (ins imemAny:$src),
1473 multiclass LDG_G<string TyStr, NVPTXRegClass regclass> {
1474 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1477 def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1480 def avar: NVPTXInst<(outs regclass:$result), (ins imemAny:$src),
1483 def ari : NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1486 def ari64 : NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1511 multiclass VLDG_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1512 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1515 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1518 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1521 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1524 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1529 multiclass VLDG_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1530 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1531 regclass:$dst4), (ins Int32Regs:$src),
1533 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1534 regclass:$dst4), (ins Int64Regs:$src),
1536 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1537 regclass:$dst4), (ins MEMri:$src),
1539 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1540 regclass:$dst4), (ins MEMri64:$src),
1542 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1543 regclass:$dst4), (ins imemAny:$src),
