Lines Matching defs:Opcode
105 /// rotate and mask opcode and mask operation.
173 /// Reg in an asm, because the load or store opcode would have to change.
339 // opcode and that it has a immediate integer right operand.
380 unsigned Opcode = N->getOpcode();
385 if (Opcode == ISD::SHL) {
390 } else if (Opcode == ISD::SRL) {
397 } else if (Opcode == ISD::ROTL) {
1075 unsigned Opcode;
1082 case MVT::f64: Opcode = PPC::LFDU; break;
1083 case MVT::f32: Opcode = PPC::LFSU; break;
1084 case MVT::i32: Opcode = PPC::LWZU; break;
1085 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1087 case MVT::i8: Opcode = PPC::LBZU; break;
1094 case MVT::i64: Opcode = PPC::LDU; break;
1095 case MVT::i32: Opcode = PPC::LWZU8; break;
1096 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1098 case MVT::i8: Opcode = PPC::LBZU8; break;
1105 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1109 unsigned Opcode;
1116 case MVT::f64: Opcode = PPC::LFDUX; break;
1117 case MVT::f32: Opcode = PPC::LFSUX; break;
1118 case MVT::i32: Opcode = PPC::LWZUX; break;
1119 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1121 case MVT::i8: Opcode = PPC::LBZUX; break;
1129 case MVT::i64: Opcode = PPC::LDUX; break;
1130 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
1131 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1133 case MVT::i8: Opcode = PPC::LBZUX8; break;
1140 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1253 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
1254 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
1658 unsigned Opcode = MachineNode->getMachineOpcode();
1659 switch (Opcode) {
1702 switch (Opcode) {
2008 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
2108 // inferred from the opcode; when we process it in the AsmPrinter,
