Lines Matching defs:Outs
3671 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3691 isTailCall, Outs, OutVals, Ins,
3695 isTailCall, Outs, OutVals, Ins,
3700 isTailCall, Outs, OutVals, Ins,
3708 const SmallVectorImpl<ISD::OutputArg> &Outs,
3748 unsigned NumArgs = Outs.size();
3751 MVT ArgVT = Outs[i].VT;
3752 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3755 if (Outs[i].IsFixed) {
3773 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3784 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3823 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3945 Outs,
3952 unsigned NumOps = Outs.size();
3976 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3977 EVT ArgVT = Outs[i].VT;
4058 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4062 CalculateStackSlotAlignment(Outs[i].VT, Flags, PtrByteSize);
4360 const SmallVectorImpl<ISD::OutputArg> &Outs,
4366 unsigned NumOps = Outs.size();
4397 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4398 EVT ArgVT = Outs[i].VT;
4496 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4702 EVT ArgType = Outs[i].VT;
4751 const SmallVectorImpl<ISD::OutputArg> &Outs,
4756 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4762 const SmallVectorImpl<ISD::OutputArg> &Outs,
4769 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
