Lines Matching refs:v2i64
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2144 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2283 case MVT::v2i64:
2635 case MVT::v2i64:
2637 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
4260 case MVT::v2i64:
4278 Arg.getSimpleValueType() == MVT::v2i64) ?
4301 Arg.getSimpleValueType() == MVT::v2i64) ?
4402 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
6011 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6014 if (Op.getValueType() == MVT::v2i64) {
6021 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6022 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
8951 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8987 if (VT == MVT::v2i64)
