Lines Matching refs:Reg
89 unsigned Reg,
93 unsigned Reg,
130 /// This functions walks the use list of Reg until it finds an Instruction
136 unsigned Reg,
138 // The Reg parameter to the function must always be defined by either a PHI
140 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
141 "Reg cannot be a physical register");
143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
162 unsigned Reg,
164 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
165 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg);
168 MachineInstr *Def = MRI.getVRegDef(Reg);
170 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
223 unsigned Reg = MI.getOperand(i).getReg();
224 const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg,
226 MRI.constrainRegClass(Reg, RC);
228 unsigned Reg = MI.getOperand(0).getReg();
229 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,
232 MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
235 if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
241 unsigned Reg = MI.getOperand(i).getReg();
242 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
