Lines Matching defs:Opcode
70 unsigned Opcode;
107 Opcode = AMDGPU::S_MOV_B32;
112 Opcode = AMDGPU::S_MOV_B32;
117 Opcode = AMDGPU::S_MOV_B32;
130 Opcode = AMDGPU::V_MOV_B32_e32;
135 Opcode = AMDGPU::V_MOV_B32_e32;
141 Opcode = AMDGPU::V_MOV_B32_e32;
147 Opcode = AMDGPU::V_MOV_B32_e32;
153 Opcode = AMDGPU::V_MOV_B32_e32;
162 get(Opcode), RI.getSubReg(DestReg, SubIdx));
171 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
174 // Try to map original to commuted opcode
175 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
178 // Try to map commuted to original opcode
179 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
182 return Opcode;
222 unsigned Opcode;
224 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
225 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
226 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
227 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
231 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
254 unsigned Opcode;
256 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
257 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
258 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
259 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
260 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
267 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
292 default: llvm_unreachable("Invalid spill opcode");
418 bool SIInstrInfo::isMov(unsigned Opcode) const {
419 switch(Opcode) {
450 int isDS(uint16_t Opcode);
454 bool SIInstrInfo::isDS(uint16_t Opcode) const {
455 return ::AMDGPU::isDS(Opcode) != -1;
458 int SIInstrInfo::isMIMG(uint16_t Opcode) const {
459 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
462 int SIInstrInfo::isSMRD(uint16_t Opcode) const {
463 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
466 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
467 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
470 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
471 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
474 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
475 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
478 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
479 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
546 uint16_t Opcode = MI->getOpcode();
547 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
548 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
549 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
552 const MCInstrDesc &Desc = get(Opcode);
600 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
634 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
643 if (isVOP3(Opcode)) {
764 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
766 Opcode = AMDGPU::COPY;
768 Opcode = AMDGPU::S_MOV_B32;
773 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
1182 unsigned Opcode = Inst->getOpcode();
1186 switch (Opcode) {
1254 // Use the new VALU Opcode.
1267 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1270 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1282 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1290 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1316 switch (Opcode) {
1369 unsigned Opcode) const {
1379 const MCInstrDesc &InstDesc = get(Opcode);
1421 unsigned Opcode) const {
1432 const MCInstrDesc &InstDesc = get(Opcode);
