Lines Matching refs:Even
299 // We want to use MVC in preference to even a single load/store pair.
1645 // on the extended Op0 and (unextended) Op1. Store the even register result
1646 // in Even and the odd register result in Odd.
1650 SDValue &Even, SDValue &Odd) {
1655 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2057 // result in the even register. SMUL_LOHI is defined to return the
2081 // result in the even register. UMUL_LOHI is defined to return the
2106 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2108 // the even register and the quotient in the odd register.
2120 // DL(G) uses a double-width dividend, so we need to clear the even
2122 // in the even register and the quotient in the odd register.
