Lines Matching refs:STD
389 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
485 static std::pair<unsigned, const TargetRegisterClass *>
486 parseRegisterNumber(const std::string &Constraint,
490 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
493 return std::make_pair(Map[Index], RC);
495 return std::make_pair(0U, nullptr);
498 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
499 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
507 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
509 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
510 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
514 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
516 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
517 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
520 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
524 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
526 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
527 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
560 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
561 std::vector<SDValue> &Ops,
838 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
858 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1606 std::swap(C.Op0, C.Op1);
2572 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
2582 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
3237 uint64_t ThisLength = std::min(Length, uint64_t(256));
3384 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3386 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
