Lines Matching defs:Opcode
610 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
624 // VEX_R: opcode externsion equivalent to REX.R in
647 // VEX_W: opcode specific (use like REX.W, or used for
648 // opcode extension, or ignored, depending on the opcode byte)
654 // 0b00001: implied 0F leading opcode
655 // 0b00010: implied 0F 38 leading opcode bytes
656 // 0b00011: implied 0F 3A leading opcode bytes
676 // VEX_PP: opcode extension providing equivalent
943 // VEX opcode prefix can have 2 or 3 bytes
973 // EVEX opcode prefix can have 4 bytes
1103 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1121 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1131 // Emit the operand size opcode prefix as needed.
1155 // 0x0F escape code must be emitted just before the opcode.
1157 case X86II::TB: // Two-byte opcode map
1178 unsigned Opcode = MI.getOpcode();
1179 const MCInstrDesc &Desc = MCII.get(Opcode);
1207 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1210 // Emit the lock opcode prefix as needed.
1214 // Emit segment override opcode prefix as needed.
1219 // Emit the repeat opcode prefix as needed.
1223 // Emit the address size opcode prefix as needed.
1275 // Emit segment override opcode prefix as needed (not for %ds).
1288 // Emit segment override opcode prefix as needed (not for %ds).
1313 // Emit segment override opcode prefix as needed.
